Patents by Inventor Jun-Sun Hwang
Jun-Sun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240007085Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.Type: ApplicationFiled: February 7, 2023Publication date: January 4, 2024Applicant: SK hynix Inc.Inventors: Dae Ho YANG, Min Su KIM, Kwan Su SHON, Keun Seon AHN, Soon Sung AN, Su Han LEE, Jae Hoon JUNG, Kyeong Min CHAE, Jae Hyeong HONG, Jun Sun HWANG
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Patent number: 11600711Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: GrantFiled: May 25, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-sun Hwang
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Patent number: 11461051Abstract: The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.Type: GrantFiled: February 23, 2021Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Jun Sun Hwang, Jung Hwan Lee, Kwan Su Shon
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Patent number: 11450366Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.Type: GrantFiled: May 27, 2021Date of Patent: September 20, 2022Assignee: SK hynix Inc.Inventors: Jin Ha Hwang, Kwang Soon Kim, Dae Ho Yang, Yo Han Jeong, Jun Sun Hwang
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Patent number: 11436152Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.Type: GrantFiled: August 14, 2020Date of Patent: September 6, 2022Assignee: SK hynix Inc.Inventors: Jin Ha Hwang, Kyeong Min Chae, Jun Sun Hwang
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Publication number: 20220270656Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.Type: ApplicationFiled: May 27, 2021Publication date: August 25, 2022Inventors: Jin Ha HWANG, Kwang Soon KIM, Dae Ho YANG, Yo Han JEONG, Jun Sun HWANG
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Publication number: 20220160999Abstract: Disclosed is a guidewire steering micro-robot. The guidewire steering micro-robot includes a guidewire, and a steering unit provided at an end portion of the guidewire, the steering unit including a magnetic body to control and steer a position of the guidewire by an external magnetic field.Type: ApplicationFiled: October 12, 2021Publication date: May 26, 2022Inventors: Hong Soo Choi, Jun Sun Hwang, Jin Young Kim, Beom Joo Kim, Hyunki Lee, Sung Jun Lim, Hwajun Jeong
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Publication number: 20220057965Abstract: The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.Type: ApplicationFiled: February 23, 2021Publication date: February 24, 2022Applicant: SK hynix Inc.Inventors: Jun Sun HWANG, Jung Hwan LEE, Kwan Su SHON
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Publication number: 20210280682Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Inventors: Jung-Gun YOU, Myung-Yoon UM, Young-Joon PARK, Jeong-Hyo LEE, Ji-Yong HA, Jun-sun HWANG
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Publication number: 20210271605Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.Type: ApplicationFiled: August 14, 2020Publication date: September 2, 2021Inventors: Jin Ha HWANG, Kyeong Min CHAE, Jun Sun HWANG
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Patent number: 11043568Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: GrantFiled: December 14, 2018Date of Patent: June 22, 2021Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-sun Hwang
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Publication number: 20190123159Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: ApplicationFiled: December 14, 2018Publication date: April 25, 2019Inventors: Jung-Gun YOU, Myung-Yoon UM, Young-Joon PARK, Jeong-Hyo LEE, Ji-Yong HA, Jun-sun HWANG
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Patent number: 10192968Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: GrantFiled: January 6, 2016Date of Patent: January 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-Sun Hwang
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Patent number: 10025506Abstract: A semiconductor device includes a plurality of semiconductor chips vertically stacked and electrically coupled to one another through TSVs (Through-Silicon Vias), a plurality of semiconductor elements formed in each of the semiconductor chips, a plurality of nodes suitable for coupling the semiconductor elements to one another, and a node control device suitable for being provided in each of the nodes, deciding whether to couple the node to a communication path based on a temperature of the node, and setting a shortest communication path among the semiconductor elements.Type: GrantFiled: March 24, 2015Date of Patent: July 17, 2018Assignees: SK Hynix Inc., Reserch & Business Foundation Sungkyunkwan UniversityInventors: Tae Hee Han, Jun Sun Hwang
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Publication number: 20170062420Abstract: A semiconductor device including a first fin pattern and a second fin pattern which have respective short sides facing each other and are separated from each other, a first field insulating layer which is around the first fin pattern and the second fin pattern, a second field insulating layer and a third field insulating layer which are between the first fin pattern and the second fin pattern, a first gate which is formed on the first fin pattern to intersect the first fin pattern, a second gate which is formed on the second field insulating layer, and a third gate which is formed on the third field insulating layer, wherein upper surfaces of the second and third field insulating layers protrude further upward than an upper surface of the first field insulating layer, and a distance between the first gate and the second gate is equal to a distance between the second gate and the third gate.Type: ApplicationFiled: July 28, 2016Publication date: March 2, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Gun YOU, Dae-Lim KANG, Myung-Yoon UM, Jeong-Hyo LEE, Jae-Yup CHUNG, Jun-Sun HWANG, Bo-Cheol JEONG
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Publication number: 20160204264Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.Type: ApplicationFiled: January 6, 2016Publication date: July 14, 2016Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-Sun Hwang
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Publication number: 20160147463Abstract: A semiconductor device includes a plurality of semiconductor chips vertically stacked and electrically coupled to one another through TSVs (Through-Silicon Vias) a plurality of semiconductor elements formed in each of the semiconductor chips, a plurality of nodes suitable for coupling the semiconductor elements to one another, and a node control device suitable for being provided in each of the nodes, deciding whether to couple the node to a communication path based on a temperature of the node, and setting a shortest communication path among the semiconductor elements.Type: ApplicationFiled: March 24, 2015Publication date: May 26, 2016Inventors: Tae Hee HAN, Jun Sun HWANG
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Patent number: 9048236Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench.Type: GrantFiled: July 22, 2013Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Jong-Mil Youn, Jong-Joon Park, Kwang-Yong Jang, Jun-Sun Hwang
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Publication number: 20140103441Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench.Type: ApplicationFiled: July 22, 2013Publication date: April 17, 2014Inventors: Ju-Youn Kim, Jong-Mil Youn, Jong-Joon Park, Kwang-Yong Jang, Jun-Sun Hwang