Patents by Inventor Jun Tajika

Jun Tajika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6777820
    Abstract: To provide a semiconductor wafer having dot marks produced by irradiating laser beam capable of selecting a marking region capable of reading and writing marks in a state in which the marks hardly vanish and the semiconductor wafer is contained in a wafer cassette, inscribing information of an identification number or electric properties in the region and grasping past history by a unit of the wafer in processing steps or semiconductor fabrication steps thereafter, a very small dot mark is formed by irradiating laser having a diameter of 1 through 13 &mgr;m on an inner wall face of a notch (1) formed on an outer peripheral face of a semiconductor wafer (W), particularly on an inclined face of its peripheral edge.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: August 17, 2004
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Teiichirou Chiba, Etsurou Satou, Jun Tajika
  • Publication number: 20030015806
    Abstract: To provide a semiconductor wafer having dot marks produced by irradiating laser beam capable of selecting a marking region capable of reading and writing marks in a state in which the marks hardly vanish and the semiconductor wafer is contained in a wafer cassette, inscribing information of an identification number or electric properties in the region and grasping past history by a unit of the wafer in processing steps or semiconductor fabrication steps thereafter, a very small dot mark is formed by irradiating laser having a diameter of 1 through 13 &mgr;m on an inner wall face of a notch (1) formed on an outer peripheral face of a semiconductor wafer (W), particularly on an inclined face of its peripheral edge.
    Type: Application
    Filed: January 27, 2000
    Publication date: January 23, 2003
    Inventors: Teiichirou Chiba, Etsurou Satou, Jun Tajika
  • Patent number: 5191798
    Abstract: A pressure sensor including a semiconductor strain gauge and resistors for compensating temperature, a zero point or the like and made of the same material as that of said semiconductor strain gauge are formed on a metal diaphragm thereof. The resistors for the compensating circuit and the strain gauge are simultaneously formed by patterning a polycrystalline silicone thin film or the like laminated on the diaphragm. As a result, the number of the elements and the manufacturing processes such as a soldering process are reduced for the purpose of improving manufacturing yield. In order to widen the zero point compensating range, a plurality of zero-point compensating resistors, if formed, are disposed on a circumference relative to the center of the diaphragm so as to reduced the scattering in the level of the resistance of each of the resistors.
    Type: Grant
    Filed: June 10, 1991
    Date of Patent: March 9, 1993
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Aki Tabata, Jun Tajika, Hiroshi Inagaki, Yukio Kobayashi, Noritake Suzuki
  • Patent number: 5167158
    Abstract: This invention provides a semiconductor film pressure sensor in which the pressure-sensitive resistance layers are made of an n-type polycrystalline silicon layer, and a method of manufacturing the sensor. In the semiconductor film pressure sensor of the invention, the pressure-sensitive resistance layers are formed on a diaphragm, and in addition a coarsely adjusting pattern and a finely adjusting pattern for zero point adjustment and the resistors of a temperature compensating circuit are formed on the diaphragm using the same n-type polycrystalline silicone layer. In formation of the n-type polycrystalline silicone layer, the substrate temperature is held at 500.degree. to 600.degree. C. The coarsely adjusting pattern and finely adjusting pattern for zero point adjustment, and the resistors of the temperature compensating circuit are formed in the same step as the pressure-sensitive resistance layers.
    Type: Grant
    Filed: March 26, 1990
    Date of Patent: December 1, 1992
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Makoto Kamachi, Jun Tajika, Aki Tabata, Noritake Suzuki, Hiroshi Inagaki
  • Patent number: 4746372
    Abstract: An amorphous silicon solar cell comprising a glass substrate, a transparent conductive film formed on the glass substrate on one side thereof and having micro-columns or fine crystals irregularly formed on the other side, a plurality of amorphous silicon layers superposed on said other side of the conductive film, and a metal electrode formed on the superposed silicon layer. At the interface between the transparent conductive film and the amorphous silicon layer is formed an intermediate layer in which both materials of the conductive film and the silicon layer are mixed. The intermediate layer has a refractive index between the conductive film and the silicon layer. The glass substrate may be substituted with a metal substrate, in which case the plurality of silicon layers are formed directly on the metal substrate, on which the transparent conductive film having an irregular surface on the side opposite to the side where the silicon layers are formed and a metal electrode are formed in this order.
    Type: Grant
    Filed: April 18, 1986
    Date of Patent: May 24, 1988
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventors: Jun Tajika, Seijiro Sano, Tsuneo Miyake, Osamu Kuboi