Patents by Inventor Jun Takaoka
Jun Takaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11961883Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: GrantFiled: May 9, 2023Date of Patent: April 16, 2024Assignee: ROHM CO. LTD.Inventor: Jun Takaoka
-
Publication number: 20230282691Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: ApplicationFiled: May 9, 2023Publication date: September 7, 2023Inventor: Jun TAKAOKA
-
Patent number: 11695036Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: GrantFiled: July 9, 2021Date of Patent: July 4, 2023Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Patent number: 11600540Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundType: GrantFiled: July 23, 2021Date of Patent: March 7, 2023Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Publication number: 20220231011Abstract: A method for manufacturing a semiconductor device is provided in which a semiconductor element that generates heat during operation is formed in an active region of a semiconductor substrate and a temperature sensitive diode sensor arranged to detect temperature is formed in a temperature sensitive diode region of the semiconductor substrate. The method includes: forming a polysilicon layer that composes the temperature sensitive diode sensor in the temperature sensitive diode region, forming a mask, and introducing impurities through the mask into the semiconductor substrate and the polysilicon layer. The mask has an element pattern having an element opening through which a region composing the semiconductor element is exposed in the active region, a diode pattern having a diode opening through which a portion of the temperature sensitive diode region is exposed, and a monitoring pattern provided within the diode pattern with a size smaller than that of the diode opening.Type: ApplicationFiled: May 21, 2020Publication date: July 21, 2022Inventor: Jun TAKAOKA
-
Publication number: 20210351091Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundType: ApplicationFiled: July 23, 2021Publication date: November 11, 2021Inventor: Jun TAKAOKA
-
Publication number: 20210335998Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventor: Jun TAKAOKA
-
Patent number: 11145714Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.Type: GrantFiled: May 31, 2019Date of Patent: October 12, 2021Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Patent number: 11101187Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes a boundary region set in a region between an active region and a current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of the second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of the second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundary region.Type: GrantFiled: October 4, 2019Date of Patent: August 24, 2021Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Patent number: 11088243Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: GrantFiled: July 8, 2020Date of Patent: August 10, 2021Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Publication number: 20200343337Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: ApplicationFiled: July 8, 2020Publication date: October 29, 2020Inventor: Jun TAKAOKA
-
Patent number: 10741637Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: GrantFiled: February 8, 2019Date of Patent: August 11, 2020Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Publication number: 20200126877Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundType: ApplicationFiled: October 4, 2019Publication date: April 23, 2020Inventor: Jun TAKAOKA
-
Publication number: 20190288062Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.Type: ApplicationFiled: May 31, 2019Publication date: September 19, 2019Inventor: Jun TAKAOKA
-
Publication number: 20190252491Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.Type: ApplicationFiled: February 8, 2019Publication date: August 15, 2019Inventor: JUN TAKAOKA
-
Patent number: 10347714Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.Type: GrantFiled: November 9, 2017Date of Patent: July 9, 2019Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Patent number: 10249751Abstract: A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer, and crystal defects are formed such that the frequency of appearance is gradually decreased from the upper surface of the p-type semiconductor layer toward the bottom surface of the n-type semiconductor layer.Type: GrantFiled: May 17, 2017Date of Patent: April 2, 2019Assignee: ROHM CO., LTD.Inventor: Jun Takaoka
-
Publication number: 20180130874Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.Type: ApplicationFiled: November 9, 2017Publication date: May 10, 2018Inventor: Jun TAKAOKA
-
Publication number: 20170338335Abstract: A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer, and crystal defects are formed such that the frequency of appearance is gradually decreased from the upper surface of the p-type semiconductor layer toward the bottom surface of the n-type semiconductor layer.Type: ApplicationFiled: May 17, 2017Publication date: November 23, 2017Inventor: Jun TAKAOKA
-
Patent number: D778679Type: GrantFiled: February 19, 2015Date of Patent: February 14, 2017Assignee: Noritake Co., LimitedInventor: Jun Takaoka