Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, a receiver section coupled to the transmitter section, and a test data analyzer coupled to the receiver section, wherein the test data analyzer includes a second pseudo-random number generator, which allows the operator to input the data value via a data bus coupled to the test data analyzer. Both the self-test data generator and the test data analyzer are independently controllable.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A device for controlling memory access in a USB interface. The device includes an interface unit for receiving data from an external source, and a memory control unit coupled to the interface unit. The memory control unit includes a microprocessor unit, a main memory unit and a shared memory unit. The microprocessor unit is capable of storing and retrieving data from the main memory unit. Both the microprocessor unit and the interface unit are capable of storing and retrieving data from the shared memory unit. The device further includes a first bus for coupling the interface unit to the microprocessor; a second bus for coupling the interface unit to the shared memory unit; and bus arbitration logic coupled to both the first bus and the second bus. The bus arbitration logic is operative for allowing the microprocessor to access the main memory unit of the memory control during the time period the interface unit is storing data in, or retrieving data from, the shared memory unit.

Abstract: A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator capable of generating a digital word. The first pseudo-random number generator is also programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, which is operable for receiving the test data and processing the test data in the same manner as any other data to be transmitted by the transmitter section. The data transceiver also includes a receiver section coupled to the transmitter section, which is operable for receiving the test data output by the transmitter section and for processing the test data in the same manner as any other data to be received by the receiver section.