Abstract: The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

Abstract: The storage interface includes a first programmable input/output unit configured to perform phase inversion on a clock signal that is output by the master controller, and output the phase-inverted clock signal to the storage device. The storage interface includes a second programmable input/output unit configured to delay a data signal that is output by the master controller, and output the delayed data signal to the storage device, where the delayed data signal is delayed by a time ?T relative to the clock signal that is output by the master controller, and TCLK/2??T?TISU and ?T?TIH, where TCLK represents a period of the clock signal, TISU represents a shortest input setup time required by the storage device in each of different data rate modes, and TIH represents a shortest input hold time employed by the storage device in each of different data rate modes.

Abstract: The storage interface includes a first programmable input/output unit; configured to perform phase inversion on a clock signal that is output by the master controller, and output the phase-inverted clock signal to the storage device. The storage interface includes a second programmable input/output unit configured to delay a data signal that is output by the master controller, and output the delayed data signal to the storage device, where the delayed data signal is delayed by a time ?T relative to the clock signal that is output by the master controller, and TCLK/2??T?TISU and ?T?TIH, where TCLK represents a period of the clock signal, TISU represents a shortest input setup time required by tire storage device in each of different data rate modes, and TIH represents a shortest input hold time employed by the storage device in each of different data rate modes.

Abstract: Provided are an array substrate, a display panel and a driving device. In the array substrate, a pressure sensor is disposed between adjacent two of the shift registers at either of the two sides of the display region; the scanning lines include a first set of scanning lines and a second set of scanning lines; the extending lines of the first set of scanning lines pass the pressure sensors in the first region, and the first set of scanning lines are electrically connected to the corresponding shift registers in the second region.

Abstract: A touch control display panel and a touch control display device are provided. The touch control display panel comprises a shift register including a plurality of cascaded shift register units, wherein a scanning line is electrically connected to an output terminal of a shift register unit; a touch driving electrode array including a plurality of touch driving electrodes; a touch switching control circuit and a plurality of touch signal lines, wherein a touch signal line has one end electrically connected to a touch driving electrode and the other end electrically connected to an output terminal of the touch switching control circuit; and a touch signal control line cluster including a plurality of touch signal control lines, wherein a touch signal control line has one end electrically connected to the output terminal of the shift register unit, and the other end electrically connected to the touch switching control circuit.

Abstract: Provided are an array substrate, a display panel and a driving device. In the array substrate, a pressure sensor is disposed between adjacent two of the shift registers at either of the two sides of the display region; the scanning lines include a first set of scanning lines and a second set of scanning lines; the extending lines of the first set of scanning lines pass the pressure sensors in the first region, and the first set of scanning lines are electrically connected to the corresponding shift registers in the second region.

Abstract: A touch control display panel and a touch control display device are provided. The touch control display panel comprises a shift register including a plurality of cascaded shift register units, wherein a scanning line is electrically connected to an output terminal of a shift register unit; a touch driving electrode array including a plurality of touch driving electrodes; a touch switching control circuit and a plurality of touch signal lines, wherein a touch signal line has one end electrically connected to a touch driving electrode and the other end electrically connected to an output terminal of the touch switching control circuit; and a touch signal control line cluster including a plurality of touch signal control lines, wherein a touch signal control line has one end electrically connected to the output terminal of the shift register unit, and the other end electrically connected to the touch switching control circuit.

Abstract: The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.