Abstract: The present invention provides a compound exhibiting coronavirus 3CL protease inhibitory activity or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same.

Abstract: According to one embodiment, an information processing device includes one or more hardware processors configured to function as a generation unit, an identification unit, and a vulnerability risk level calculation unit. The generation unit generates dependence information including an execution user of a first evaluation target and a dependence relationship representing being in a dependence relationship with the first evaluation target and access authority information of a resource. The identification unit identifies a resource accessible by the first evaluation target based on the execution user and the access authority information. The vulnerability risk level calculation unit calculates a vulnerability risk level indicating a risk level of each vulnerability from the resource accessible by the first evaluation target and one or more pieces of vulnerability information.

Abstract: According to one embodiment, an information processing device includes one or more processors. The one or more processors are configured to: detect, from a plurality of target components included in an information processing system to be evaluated, one or more of first components affected by a vulnerability included in the information processing system; specify, by using assessment information that associates at least some of the plurality of target components, one or more of assets included in the information processing system, and a degree of impact when the one or more of the assets are attacked, the one or more of the assets corresponding to the detected one or more of the first components; and obtain an evaluation value of damage when the vulnerability is attacked, based on the degree of impact corresponding to the specified one or more of the assets.

Abstract: A circuit device includes: a first phase comparison circuit including a sampling circuit that samples a feedback signal based on a reference clock signal; a first charge pump circuit configured to output a current corresponding to a sampling voltage; a second phase comparison circuit including a dead zone detection circuit that detects whether a phase difference between the reference clock signal and a feedback clock signal falls within a dead zone, and configured to output a phase difference signal when the phase difference does not fall within the dead zone; a second charge pump circuit; and a clock signal generation circuit configured to generate the clock signal having a frequency controlled based on an output of the first charge pump circuit or the second charge pump circuit. The second charge pump circuit is set disabled or in a low power consumption mode in a dead zone period.

Abstract: A circuit device includes a first terminal, a first oscillation circuit oscillating a resonator and generating a first voltage for automatic gain control for controlling amplitude of a signal output from the resonator, a digital signal generation circuit generating a digital signal corresponding to the first voltage, and a first interface circuit outputting the digital signal to the first terminal.

Abstract: A circuit device includes: a first phase comparison circuit including a sampling circuit that samples a feedback signal based on a reference clock signal; a first charge pump circuit configured to output a current corresponding to a sampling voltage; a second phase comparison circuit including a dead zone detection circuit that detects whether a phase difference between the reference clock signal and a feedback clock signal falls within a dead zone, and configured to output a phase difference signal when the phase difference does not fall within the dead zone; a second charge pump circuit; and a clock signal generation circuit configured to generate the clock signal having a frequency controlled based on an output of the first charge pump circuit or the second charge pump circuit. The second charge pump circuit is set disabled or in a low power consumption mode in a dead zone period.

Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.

Abstract: A circuit device includes a first terminal, a first oscillation circuit oscillating a resonator and generating a first voltage for automatic gain control for controlling amplitude of a signal output from the resonator, a digital signal generation circuit generating a digital signal corresponding to the first voltage, and a first interface circuit outputting the digital signal to the first terminal.

Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.

Abstract: Provided is an oscillator including: a resonator; a first circuit device electrically coupled to the resonator; and a second circuit device. The first circuit device generates a first clock signal by causing the resonator to oscillate, and performs first temperature compensation processing for temperature compensating a frequency of the first clock signal. The second circuit device receives the first clock signal from the first circuit device, generates a second clock signal based on the first clock signal, and performs second temperature compensation processing for temperature compensating a frequency of the second clock signal.

Abstract: An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, a control terminal that is electrically coupled to the circuit device, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit and sets a potential of the control terminal to an abnormality detection voltage when an abnormal state is detected by the abnormality detection circuit.

Abstract: An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit, and when an abnormal state is detected by the abnormality detection circuit, the circuit device changes a signal characteristic of the clock signal.

Abstract: Provided is an oscillator including: a resonator; a first circuit device electrically coupled to the resonator; and a second circuit device. The first circuit device generates a first clock signal by causing the resonator to oscillate, and performs first temperature compensation processing for temperature compensating a frequency of the first clock signal. The second circuit device receives the first clock signal from the first circuit device, generates a second clock signal based on the first clock signal, and performs second temperature compensation processing for temperature compensating a frequency of the second clock signal.

Abstract: An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit, and when an abnormal state is detected by the abnormality detection circuit, the circuit device changes a signal characteristic of the clock signal.

Abstract: An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, a control terminal that is electrically coupled to the circuit device, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit and sets a potential of the control terminal to an abnormality detection voltage when an abnormal state is detected by the abnormality detection circuit.

Abstract: A composite sensor includes a first sensor outputting a first sensor signal, a second sensor outputting a second sensor signal, a circuit board electrically connected to the first and second sensors, and a mount member having one surface on which the first and second sensors and the circuit board are disposed. The first and second sensors have respective input terminals to which respective input signals are inputted, and have respective output terminals from which the first and second sensor signals are outputted. When a virtual straight line passing respective centers of the first and second sensors parallel to an arrangement direction of the sensors is defined, the respective input terminals of the first and second sensors are disposed in one of two regions divided by the virtual line, and the respective output terminals of the first and second sensors are disposed in a remaining one of the two regions.

Abstract: A composite sensor includes a first sensor outputting a first sensor signal, a second sensor outputting a second sensor signal, a circuit board electrically connected to the first and second sensors, and a mount member having one surface on which the first and second sensors and the circuit board are disposed. The first and second sensors have respective input terminals to which respective input signals are inputted, and have respective output terminals from which the first and second sensor signals are outputted. When a virtual straight line passing respective centers of the first and second sensors parallel to an arrangement direction of the sensors is defined, the respective input terminals of the first and second sensors are disposed in one of two regions divided by the virtual line, and the respective output terminals of the first and second sensors are disposed in a remaining one of the two regions.

Abstract: A circuit device includes first and second detection circuits which detect physical quantity signals based on detection signals from first and second physical quantity transducers, a multiplexer which selects any one signal among a plurality of signals including the physical quantity signals from the first and second detection circuits, an A/D conversion circuit which performs A/D conversion of the selected signal, and a logic circuit which performs processing of a digital signal from the A/D conversion circuit. The first detection circuit is arranged on a second direction side from a first side of the circuit device. The second detection circuit is arranged on the second direction side from the first side and on a first direction side from the first detection circuit. The A/D conversion circuit is arranged between at least one of the first or second detection circuit and the logic circuit.

Abstract: An object of the invention is to provide a hair dye composition containing an oxidation dye or a direct dye which has excellent emulsion stability. In order to achieve the object, a hair dye composition containing a surfactant having a sterol skeleton is provided. As a result, a hair dye composition containing an oxidation dye or a direct dye having excellent emulsion stability can be obtained.

Abstract: A circuit device includes a multiplexer that selects an input signal from first to n-th input signals in a time division manner and outputs the selected input signal to an output node, an A/D conversion circuit that receives the first to n-th input signals outputted from the multiplexer to the output node in a time division manner and A/D-converts the received first to n-th input signals in a time division manner, and a buffer circuit provided between an i-th input node and the output node of the multiplexer. The buffer circuit buffers the i-th input signal and outputs the buffered signal to the output node of the multiplexer in a first period. The multiplexer selects the i-th input signal and outputs the selected signal to the output node in a second period. End timing of the second period comes after end timing of the first period.