Patents by Inventor Jun Ueshima

Jun Ueshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11435928
    Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 6, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Ueshima, Takahiro Okada, Tadaaki Yuba, Ken Matsumoto, Shinichi Tsuchida
  • Patent number: 11080167
    Abstract: A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 3, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takahiro Okada, Tadaaki Yuba, Jun Ueshima, Shinichi Tsuchida, Ken Matsumoto
  • Publication number: 20190361796
    Abstract: A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.
    Type: Application
    Filed: December 14, 2017
    Publication date: November 28, 2019
    Inventors: TAKAHIRO OKADA, TADAAKI YUBA, JUN UESHIMA, SHINICHI TSUCHIDA, KEN MATSUMOTO
  • Publication number: 20190347030
    Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.
    Type: Application
    Filed: October 13, 2017
    Publication date: November 14, 2019
    Inventors: Jun Ueshima, Takahiro Okada, Tadaaki Yuba, Ken Matsumoto, Shinichi Tsuchida
  • Patent number: 7502077
    Abstract: A video signal-processing device that can improve the apparent contrast of the luminance signal at a television receiving set includes a quantity of black expansion computing section for computationally determining the quantity of black expansion when the luminance component of the input video signal is not higher than a first luminance level, a gain controller for regulating the quantity of black expansion as computationally determined by the quantity of black expansion computing section, a quantity of black expansion adding section for generating an output video signal by adding the quantity of black expansion regulated by the gain controller to the luminance component of the input video signal, and a vertical span adding block for integrating the luminance component of the output video signal not higher than a second luminance level for a field.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 10, 2009
    Assignee: Sony Corporation
    Inventors: Satoshi Miura, Takatomo Nagamine, Yumiko Mito, Jun Ueshima
  • Patent number: 7355653
    Abstract: When an A/D-converted composite video signal is directly outputted while a system clock frequency is switched so as to execute the determination of a signal system, a digital chroma demodulation system prevents the images displayed by the composite video signals from being distorted in accordance with a switching of the frequency of a system clock. The frequency m (=fsc×n) of the system clock is synchronized with a color burst signal and is set to fall in a predetermined range by changing a coefficient n in accordance with the system color burst signal freguency. Thus, since a composite video signal is A/D-converted in accordance with a substantially constant sampling frequency, the sampling condition such as a sampling frequency and a sampling point is not greatly changed.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: April 8, 2008
    Assignee: Sony Corporation
    Inventors: Takatomo Nagamine, Takahiko Tamura, Jun Ueshima
  • Publication number: 20050157212
    Abstract: A video signal-processing device that can improve the apparent contrast of the luminance signal at a television receiving set includes a quantity of black expansion computing section for computationally determining the quantity of black expansion when the luminance component of the input video signal is not higher than a first luminance level, a gain controller for regulating the quantity of black expansion as computationally determined by the quantity of black expansion computing section, a quantity of black expansion adding section for generating an output video signal by adding the quantity of black expansion regulated by the gain controller to the luminance component of the input video signals and a vertical span adding block for integrating the luminance component of the output video signal not higher than a second luminance level for a field.
    Type: Application
    Filed: June 24, 2003
    Publication date: July 21, 2005
    Inventors: Satoshi Miura, Takatomo Nagamine, Yumiko Mito, Jun Ueshima
  • Patent number: 5909258
    Abstract: In a CRT display and a television set having the same, horizontal/vertical synchronizing signals are separated from a video synchronizing signal in a synchronizing separation circuit, and position information S of a vertical frame is generated on the basis of the horizontal/vertical synchronizing signals in a count-down processor and then converted to corrected vertical frame information W in a function circuit to output a vertical deflection waveform signal and a horizontal deflection correcting waveform signal. Further, the corrected vertical frame information W is compared with predetermined voltages in comparators to detect an effective frame range in the vertical direction.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: June 1, 1999
    Assignee: Sony Corporation
    Inventors: Akira Shirahama, Takahiko Tamura, Jun Ueshima
  • Patent number: 5745001
    Abstract: An active filter apparatus makes it possible for a filter adjusting circuit to require a small number of elements when the filter adjusting circuit is contained in an integrated circuit, to be not easily affected by variations in the characteristics of the elements which form the circuit, and to be capable of easily adjusting the frequency characteristics of the filter to be adjusted. A characteristics conversion device converts, on the basis of an input signal and an output signal of the filter, to a characteristics conversion signal whose amplitude when the adjustment is completed is considerably larger than that of the output signal. As a result, the amplification factor of the characteristics conversion device, necessary to detect a maximum or minimum value of a characteristics conversion signal, is considerably small. Therefore, it is possible to considerably decrease an offset error of the characteristics conversion device.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: April 28, 1998
    Assignee: Sony Corporation
    Inventors: Jun Ueshima, Katsunori Sato, Yoshiyuki Takayanagi, Hideki Hirose
  • Patent number: 5146108
    Abstract: A parabolic wave generator in a color television receiver or the like wherein, when the amplitude level of an input sawtooth wave is higher than the center level thereof, squared currents of mutually reverse polarities obtained by squaring the difference current proportional to the difference voltage between the two levels are added to each other at a predetermined rate, so that one side portion of a nonsymmetrical parabolic wave is produced. Meanwhile, when the amplitude level of the input sawtooth wave is lower than the center level thereof, squared currents of mutually reverse polarities obtained by squaring the difference current proportional to the difference voltage between the two levels are added to each other at another predetermined rate to thereby produce the other portion of the parabolic wave. Consequently it becomes possible to generate the two side portions of mutually different waveforms.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: September 8, 1992
    Assignee: Sony Corporation
    Inventors: Takahiko Tamura, Jun Ueshima