Patents by Inventor Jun W. Chen
Jun W. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5618743Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: June 5, 1995Date of Patent: April 8, 1997Assignee: Siliconix incorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5583061Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: June 5, 1995Date of Patent: December 10, 1996Assignee: Siliconix incorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5559044Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: October 17, 1994Date of Patent: September 24, 1996Assignee: Siliconix incorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5547880Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: June 5, 1995Date of Patent: August 20, 1996Assignee: Siliconix IncorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5541123Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: June 5, 1995Date of Patent: July 30, 1996Assignee: Siliconix IncorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5541125Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: June 5, 1995Date of Patent: July 30, 1996Assignee: Siliconix incorporatedInventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
-
Patent number: 5521409Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.Type: GrantFiled: December 22, 1994Date of Patent: May 28, 1996Assignee: Siliconix IncorporatedInventors: Fwu-Iuan Hshieh, Mike Chang, Jun W. Chen, King Owyang, Dorman C. Pitzer, Jan Van Der Linde
-
Patent number: 5451533Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.Type: GrantFiled: October 5, 1994Date of Patent: September 19, 1995Assignee: Siliconix incorporatedInventors: Richard K. Williams, Kevin Jew, Jun W. Chen
-
Patent number: 5429964Abstract: A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.Type: GrantFiled: January 12, 1994Date of Patent: July 4, 1995Assignee: Siliconix incorporatedInventors: Hamza Yilmaz, Fwu-Iuan Hshieh, Mike Chang, Jun W. Chen, King Owyang, Dorman C. Pitzer, Jan Van Der Linde
-
Patent number: 5426328Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: April 11, 1994Date of Patent: June 20, 1995Assignee: Siliconix incorporatedInventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
-
Patent number: 5422508Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: March 5, 1993Date of Patent: June 6, 1995Assignee: Siliconix IncorporatedInventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
-
Patent number: 5420451Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.Type: GrantFiled: November 30, 1993Date of Patent: May 30, 1995Assignee: Siliconix incorporatedInventors: Richard K. Williams, Kevin Jew, Jun W. Chen
-
Patent number: 5416039Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: April 8, 1994Date of Patent: May 16, 1995Assignee: Siliconix IncorporatedInventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
-
Patent number: 5404040Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.Type: GrantFiled: July 22, 1993Date of Patent: April 4, 1995Assignee: Siliconix incorporatedInventors: Fwu-Iuan Hshieh, Mike Chang, Jun W. Chen, King Owyang, Dorman C. Pitzer, Jan V. D. Linde
-
Patent number: 5374569Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.Type: GrantFiled: March 5, 1993Date of Patent: December 20, 1994Assignee: Siliconix IncorporatedInventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
-
Patent number: 5304831Abstract: A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.Type: GrantFiled: May 12, 1992Date of Patent: April 19, 1994Assignee: Siliconix IncorporatedInventors: Hamza Yilmaz, Fwu-Iuan Hshieh, Mike Chang, Jun W. Chen, King Owyang, Dorman C. Pitzer, Jan Van Der Linde