Patents by Inventor Jun Wada

Jun Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compound semiconductor device having a reduced source resistance
    Patent number: 6242327
    Abstract: A compound semiconductor device includes a low resistance source and drain region covered by a protective layer of a compound semiconductor device carrying thereon a source electrode or a drain electrode. Further, a low resistance source and drain region formed by a regrowth process of a compound semiconductor material is disclosed.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: June 5, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsunori Yokoyama, Hitoshi Tanaka, Jun Wada
  • Semiconductor device with metallic protective film
    Patent number: 5923072
    Abstract: A semiconductor device has a metal pattern composed of a material reacting on water and a metal protective film formed between an intrusion path of water and the metal pattern on the surface of a part of the metal pattern. The metal pattern is composed of a refractory metal, a refractory metal compound or aluminum, and the metal protective film is formed of any of gold, platinum, palladium, gold alloy, platinum alloy, palladium alloy and lanthanum hexaboron.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 13, 1999
    Assignee: Fujitsu Limited
    Inventors: Jun Wada, Toshihiro Ogihara
  • MES field effect transistor possessing lightly doped drain
    Patent number: 5532507
    Abstract: In a MESFET of this invention possessed of an LDD structure, a current control layer possessed of conduction type opposite to that of an active layer is formed below the active layer. In the part of this current control layer underlying a gate electrode, a low impurity concentration region destined to function as a channel region for a transistor is formed. Further, LDD regions are formed at both sides of the channel region. In the current control layer, the part underlying the channel region is kept at a low impurity concentration while the other parts underlying the LDD regions are kept at a higher impurity concentration than the part underlying the channel region. Thus, a MESFET possessed of an improved short channel effect and excellent high frequency characteristics is obtained.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: July 2, 1996
    Assignee: Fujitsu Limited
    Inventor: Jun Wada
  • Pastes for forming a luminescent layer and insulator layer of electroluminescent element and electroluminescent element using such pastes
    Patent number: 5076963
    Abstract: The present invention discloses an electroluminescent element comprising spherical spacer particles in a luminescent layer having a dielectric constant of not less than 10 at 1 KHz and 25.degree. C. and an insulator layer having a dielectric constant of not less than 10 at 1 KHz and 25.degree. C. which both layers are disposed between a transparent electrode and a back electrode, either of said luminescent layer or of said insulator layer having been produced by forming a phosphor paste layer or an insulative paste layer and solidifying each with radiation, respectively.
    Type: Grant
    Filed: April 24, 1990
    Date of Patent: December 31, 1991
    Assignees: Nippon Kasei Chemical Co., Ltd, Nitto Denko Corporation
    Inventors: Akinori Kameyama, Jun Wada, Yutaka Nakabayashi