Abstract: A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit.

Abstract: A defect signal generating circuit comprises a low pass filter circuit which receives an input signal whose signal level is changed from a reference level to a higher level or a lower level corresponding to a dark defect or a bright defect of a optical disk, and outputs a low pass filter signal having a time constant longer than the input signal; an operation circuit which operates a difference between a level of the input signal and a level of the low pass filter signal, and outputs a first operation value; a defect determination circuit which determines whether a defect is the dark defect or the bright defect on the basis of the sign of the first operation value; a defect detection determination circuit which compares the absolute value of the first operation value with the absolute value of a first reference value, and determines that a defect is detected when the absolute value of the first operation value is larger than the absolute value of the first reference value; and an output circuit which outputs

Abstract: A processor system, comprising: a first program storage which stores a first program; a second program storage which stores a second program; a program counter which outputs execution addresses of said first and second programs; a first address storage which stores a first address in said first program; a second address storage which stores a second address in said second program; a comparator which compares whether or not said program counter coincides with said first address; an address changing unit which changes said program counter to said second address, when it is determined to have coincided by said comparator; and a data bus which updates said first address stored in said first address storage and said second address stored in said second address storage.

Abstract: A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit

Abstract: A data reproducing device disclosed herein comprises: a disk analysis executor which performs a disk analysis of analyzing a file and directory structure of a record medium; a detection judgment section which judges whether or not a predetermined number of files and/or a predetermined number of directories including a file is detected by the disk analysis executor; and a reproduction starter which suspends the disk analysis and starts reproduction of data of the detected file when the detection judgment section judges that the predetermined number of files and/or the predetermined number of directories including the file is detected.

Abstract: A processor system, comprising: a first program storage which stores a first program; a second program storage which stores a second program; a program counter which outputs execution addresses of said first and second programs; a first address storage which stores a first address in said first program; a second address storage which stores a second address in said second program; a comparator which compares whether or not said program counter coincides with said first address; an address changing unit which changes said program counter to said second address, when it is determined to have coincided by said comparator; and a data bus which updates said first address stored in said first address storage and said second address stored in said second address storage.

Abstract: An apparatus for storing and reproducing data includes a detector to detect available space in a storage medium in which target data is configured to be stored, an estimator to estimate a compressed quantity of the target data if the target data is compressed at an initial bit rate, a comparator to compare the detected available space with the estimated quantity and provide a comparison result, and a DSP to determine a bit rate according to the comparison result, compress the target data at the determined bit rate, and configured to store the compressed data in the storage medium.

Abstract: The present invention discloses reproduction pitch change technology incorporated in audio reproduction system capable of changing reproduction pitch or reproduction time of reproduced sound without causing enlargement of the configuration of the system and complicatedness of its processing and damaging the quality of the reproduced sound. When inputted audio data is converted inversely from frequency region to time region the spectrum of the inputted audio data is shifted on the frequency axis based on a reproduction pitch changing amount and a band width of the audio data after the shift is matched to the band width of the inputted audio data before the shift to obtain a reproduction frequency of the time-series audio data to be outputted.