Abstract: A display apparatus includes: a substrate including a display area, in which a first pixel and a second pixel respectively emitting light of different wavelengths from each other are disposed, and a peripheral area; a first common voltage line disposed in the display area and including a plurality of pad units spaced apart from each other by a predetermined interval; a second common voltage line disposed in the display area and extending in a second direction to overlap the second pixel; and a third common voltage line disposed in the display area and extending in the second direction to overlap the first pixel, where the second common voltage line is electrically connected to the plurality of pad units of the first common voltage line through a contact portion in an area where the second common voltage line overlaps the plurality of pad units.

Abstract: A display device includes a first lower active pattern, a first lower gate electrode disposed on the first lower active pattern and forming a storage capacitor together with the lower active pattern, a second lower gate electrode disposed on the first lower gate electrode and forming a first compensation capacitor together with the first lower gate electrode, an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode, and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern.

Abstract: A display device includes: a substrate including a display area and a non-display area including a pad area; an inorganic insulating layer disposed on the substrate and including a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer; a light-emitting element layer disposed on the inorganic insulating layer and including a light-emitting element overlapping the display area in a plan view; a gate wiring overlapping the display area in the plan view, extending in a first direction and disposed between the first inorganic insulating layer and the second inorganic insulating layer; and a fanout wiring extending in a direction toward the display area from the pad area and disposed between the second inorganic insulating layer and the third inorganic insulating layer, where a sheet resistance of the gate wiring is lower than a sheet resistance of the fanout wiring.

Abstract: An electronic device includes: a display panel including a circuit layer, and a light emitting element layer. The circuit layer includes: a base layer; a transistor on the base layer; a connecting electrode electrically connected with the transistor; and a plurality of data lines above the transistor. The light emitting element layer includes: a first anode on the circuit layer, and electrically connected with the connecting electrode; a first emissive layer on the first anode; and a cathode on the first emissive layer. The plurality of data lines includes: a first data line extending in a first direction; a second data line spaced from the first data line in a second direction crossing the first direction; and a third data line spaced from the second data line in the second direction. Each of the plurality of data lines overlaps with the first anode in a plan view.

Abstract: A display device including a base layer, a circuit layer including 1-1 and 1-2 pixel circuits, and a light emitting element layer including first and second light emitting elements each including a first electrode, an emission layer, a second electrode, and a pixel defining film. The 1-1 pixel circuit and the 1-2 pixel circuit each include a driving and a gate conductive layer. An area in which the first electrode of the first light emitting element overlaps the gate conductive layer of the 1-1 pixel circuit in plan view is equal to an area in which the first electrode of the second light emitting element overlaps the gate conductive layer of the 1-2 pixel circuit in plan view.

Abstract: A display apparatus includes substrate a semiconductor layer on the substrate, and having a semiconductor pattern, a first conductive layer on the semiconductor layer, and including a first wiring that extends in a first direction, a second wiring that protrudes from the first wiring in a second direction crossing the first direction, and a driving gate electrode, and a second conductive layer on the first conductive layer, and including a first electrode that overlaps the driving gate electrode, wherein the semiconductor pattern includes a first pattern that extends in the first direction and overlaps the second wiring, and a second pattern that extends in the second direction and overlaps the first wiring, and wherein the first electrode includes a protruding electrode that overlaps at least part of the first pattern and at least part of the second pattern.

Abstract: A pixel includes a first transistor including a first and second gates, a first capacitor connected between a first node and a third node, a second capacitor connected between a fourth node and the third node, a second transistor receiving a first scan signal and connected between a data line and the first node, a third transistor receiving a second scan signal and connected between a reference voltage line and the first node, a fourth transistor receiving a third scan signal and connected between an initialization line and the third node, a fifth transistor receiving an emission signal and connected between a first power line and the second node, a sixth transistor receiving the second scan signal and connected between the fourth node and the second node, and a light emitting element connected between the third node and a second power line.

Abstract: A display panel includes a plurality of pixel circuits disposed in a display area, and a scan driver disposed in a peripheral area adjacent to the display area and including a first driving circuit and a second driving circuit. The first driving circuit includes a plurality of first stages that outputs first scan signals to the plurality of pixel circuits, and the second driving circuit includes a plurality of second stages that outputs second scan signals to the plurality of pixel circuits. The plurality of first stages are disposed in odd-numbered rows and the plurality of second stages are disposed in even-numbered rows.

Abstract: A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a power supply line arranged in the peripheral area, a gate driving circuit arranged between the power supply line and the display area and including a plurality of stages arranged in a direction, and a signal line arranged in the peripheral area, electrically connected to a first stage from among the plurality of stages of the gate driving circuit, and configured to transmit a start signal, wherein the signal line overlaps the power supply line in a plan view and is arranged between the substrate and the power supply line.

Abstract: A display device includes: a display panel; a first light emitting driving circuit to provide first emission signals; and a second light emitting driving circuit to provide second emission signals. The display panel includes: a plurality of pixels, each including a first light emitting element and a second light emitting element; and a light control pattern overlapping with the second light emitting element of each of the plurality of pixels in a plan view. Each of the plurality of pixels is to emit light through the first light emitting element when a corresponding first emission signal is at an active level, and emit light through the second light emitting element when a corresponding second emission signal is at the active level. A part of the first emission signals and the second emission signals remains at an inactive level during at least one frame based on an operating mode.

Abstract: A display device includes a first lower active pattern, a first lower gate electrode disposed on the first lower active pattern and forming a storage capacitor together with the lower active pattern, a second lower gate electrode disposed on the first lower gate electrode and forming a first compensation capacitor together with the first lower gate electrode, an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode, and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern.

Abstract: A display device includes a plurality of pixels. A power line is connected to the plurality of pixels. The power line includes a plurality of horizontal power lines extending in a first direction and arranged in a second direction crossing the first direction and a plurality of vertical power lines extending in the second direction and arranged in the first direction. The plurality of vertical power lines cross the plurality of horizontal power lines when viewed from above a plane. The plurality of horizontal power lines is alternately connected to two adjacent vertical power lines of the plurality of vertical power lines.

Abstract: A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a power supply line arranged in the peripheral area, a gate driving circuit arranged between the power supply line and the display area and including a plurality of stages arranged in a direction, and a signal line arranged in the peripheral area, electrically connected to a first stage from among the plurality of stages of the gate driving circuit, and configured to transmit a start signal, wherein the signal line overlaps the power supply line in a plan view and is arranged between the substrate and the power supply line.

Abstract: A display device includes a base layer, a pixel circuit disposed on the base layer and comprising a plurality of pixel transistors, a gate insulating layer covering the first and second oxide semiconductor patterns, and a light emitting element electrically connected to the pixel circuit. The pixel transistors include a first pixel transistor including a first oxide semiconductor pattern and a second pixel transistor including a second oxide semiconductor pattern. An open area is defined through the gate insulating layer to correspond to a first source and a first drain of the first oxide semiconductor pattern.

Abstract: A display apparatus is disclosed that includes a substrate, an additional transistor, a first wiring, a first insulating layer, and a second wiring. The additional transistor is located on the substrate and includes an additional semiconductor layer and an additional gate electrode. The first wiring is integrally formed with the additional gate electrode and extends in a first direction. The first insulating layer is located on the first wiring. The second wiring is located on the first insulating layer and extends in a second direction intersecting the first direction. The second wiring is connected to a source region and a drain region of the additional semiconductor layer.

Abstract: A display device is disclosed that includes a first active layer, a gate pattern, a second active layer, and a lower conductive layer. The first active layer is disposed on a substrate. The gate pattern is disposed on the first active layer. The second active layer is disposed on the gate pattern and includes a body portion electrically connected to the gate pattern. The lower conductive layer is disposed between the substrate and the first active layer and includes a first region. At least a part of the first region overlaps an entirety of the body portion of the second active layer.

Abstract: A display device includes first to fifth data lines, a sub-pixel array including first sub-pixels, second sub-pixels, and third sub-pixels, and a lighting test circuit. The sub-pixel array includes a first sub-pixel column disposed adjacent to the first data line and in which first sub-pixels connected to the first data line and third sub-pixels connected to the third data line are alternately arranged, and a third sub-pixel column disposed adjacent to the third data line and in which third sub-pixels connected to the third data line and first sub-pixels connected to the fifth data line are alternately arranged. The lighting test circuit includes a first transistor which outputs a first test voltage to the first data line, and a third transistor which outputs a third test voltage to the third data line.

Abstract: Provided is a display panel including a substrate including a display area, an opening area within the display area, and an intermediate area between the opening area and the display area, a light-emitting diode in the display area, and including a sub-pixel electrode, an opposite electrode above the sub-pixel electrode, and an intermediate layer between the sub-pixel electrode and the opposite electrode, an organic pattern layer in the intermediate area above the substrate, and defining a first groove and a second groove, a conductive pattern layer in the second groove, and including a tip having an end protruding toward a center of the first groove in plan view, and a line electrically connected to the conductive pattern layer, and passing through the display area.

Abstract: A display apparatus includes first initialization voltage lines extending in a first direction, second initialization voltage lines extending in the first direction, first initialization connection lines extending in a second direction intersecting the first direction and electrically connecting the first initialization voltage lines to each other, second initialization connection lines extending in the second direction and electrically connecting the second initialization voltage lines to each other, and pixels connected to the first initialization voltage lines, the second initialization voltage lines, the first initialization connection lines and the second initialization connection lines.

Abstract: A display device is disclosed that includes a first active layer, a gate pattern, a second active layer, and a lower conductive layer. The first active layer is disposed on a substrate. The gate pattern is disposed on the first active layer. The second active layer is disposed on the gate pattern and includes a body portion electrically connected to the gate pattern. The lower conductive layer is disposed between the substrate and the first active layer and includes a first region. At least a part of the first region overlaps an entirety of the body portion of the second active layer.