Patents by Inventor Jun-Yao Wang
Jun-Yao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972799Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.Type: GrantFiled: March 1, 2022Date of Patent: April 30, 2024Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Chia-Hung Lin, Jun-Yao Huang
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Publication number: 20240087644Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.Type: ApplicationFiled: August 29, 2023Publication date: March 14, 2024Applicant: Winbond Electronics Corp.Inventors: I-Hsien Tseng, Lung-Chi Cheng, Ju-Chieh Cheng, Jun-Yao Huang, Ping-Kun Wang
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Publication number: 20240090343Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
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Patent number: 8321768Abstract: In a method and system for calculating CRC, a Partial CRC is first calculated directly according to a segment of a message. Then, a First Code including the Partial CRC appended with a plurality of zero-bytes is generated. Finally, the Adjusted CRC is calculated according to the First Code. Therefore, an Adjusted CRC can be derived directly from each segment of a message. After all segments of a message are received, all the derived Adjusted CRCs are merged to obtain a Final CRC of the message. The method and system can be quickly prototyped and implemented to various systems due to its simplicity.Type: GrantFiled: April 3, 2008Date of Patent: November 27, 2012Assignee: Industrial Technology Research InstituteInventors: Shen-Ming Chung, Jun-Yao Wang, Hsiao-Hui Lee
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Patent number: 8103840Abstract: A snapshot mechanism and a method thereof used in a data processing system are provided to backup snapshot data. The snapshot mechanism includes a snapshot storage unit and a buffer storage unit, wherein the snapshot storage unit is used as a unit for storing data generated after a target storage unit snapshots data and accordingly generating a plurality of snapshot management data. In addition, the buffer storage unit temporarily stores new data and flushes the data to the target storage unit in predetermined time interval. According to the snapshot management data, the target storage unit can be rolled back or rolled forward to the status before a predetermined time.Type: GrantFiled: December 6, 2006Date of Patent: January 24, 2012Assignee: Industrial Technology Research InstituteInventors: Wen-Shyang Hwang, Ching-Hung Lin, Jun-Yao Wang, Chin-Pei Su, Tsung-Lin Tsai
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Patent number: 7882315Abstract: A snapshot mechanism of a data processing system is provided herein. The snapshot mechanism includes providing a snapshot storage unit for storing the data created when snapshotting the target storage units and generating a plurality of snapshot images accordingly. Two different types of address tables in the snapshot image are used for corresponding to the storage units of the snapshot storage unit and the target storage units. The status of the target storage units can be recovered to the status at a predetermined time ago according to the snapshot images. The two types of address tables are respectively used for storing the data created by the data processing system and history data so as to prevent the data stored in the target storage units to be overwritten.Type: GrantFiled: August 10, 2006Date of Patent: February 1, 2011Assignee: Industrial Technology Research InstituteInventors: Tsung-Lin Tsai, Jun-Yao Wang, Shou-Jen Wey
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Patent number: 7747766Abstract: A method and system for recognizing offloaded packets, wherein a common attribute of connection identifications among a plurality of offloaded connections is first calculated. Then, a connection identification of a packet is recognized to determine whether the connection identification of the packet has the common attribute so as to determine whether the packet is a non-offloaded packet. Therefore, the non-offloaded packet can be promptly recognized to greatly lower the recognition workload of an embedded processor, to improve the efficiency of executing a partial offloaded process by the embedded processor and to decrease the operation delay of the non-offloaded packet in a protocol offload processing system.Type: GrantFiled: December 27, 2006Date of Patent: June 29, 2010Assignee: Industrial Technology Research InstituteInventors: Shen-Ming Chung, Jun-Yao Wang, Hsiao-Hui Lee
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Patent number: 7460550Abstract: A storage structure and method having multiple protocol processor units are disclosed. The storage structure comprises a host CPU, a main memory, a storage device, a switch fabric, and a host bus adapter module. The host bus adapter module includes a plurality of protocol processor nodes for processing frames received from a network, and storing those frames into the storage device. A processing module of the host bus adapter module extracts the session information of each frame and compares it with entries recorded in a look-up table. If the connection information hits one entry of the look-up table, the frame can be bypassed into a corresponding protocol processor node according to the definition of the look-up table. Otherwise, a new entry will be inserted into the look-up table for designating a corresponding protocol processor node.Type: GrantFiled: November 3, 2004Date of Patent: December 2, 2008Assignee: Industrial Technology Research InstituteInventors: Jun-Yao Wang, Chung-Ho Chen, Chao-Lin Su, Chao-Hsien Hsu, Cheng-Yeh Yu, I-Cheng Chung
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Patent number: 7444451Abstract: The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, and an interrupt controller. The first calculating device is used for calculating packet information of a plurality of packets. The packet header parser is used for recognizing the type of service field in each packet and for generating a minimum delay control signal. The second calculating device is used for determining a coalescing interrupt number signal according to the packet information and the minimum delay control signal. The interrupt controller is used for transmitting an interrupt control signal to process the packet according to the coalescing interrupt number signal.Type: GrantFiled: July 18, 2006Date of Patent: October 28, 2008Assignee: Industrial Technology Research InstituteInventors: Wen-Fong Wang, Jun-Yao Wang
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Publication number: 20080250297Abstract: The invention relates to a method and system for calculating CRC. Firstly, a Partial CRC is calculated directly according to a segment of a message. Then, a First Code comprising the Partial CRC appended with a plurality of zero-bytes is generated. Finally, the Adjusted CRC is calculated according to the First Code. Therefore, the method and system of the invention can derive an Adjusted CRC directly from each segment of a message. After all segments of a message are received, all the derived Adjusted CRCs are merged to obtain a Final CRC of the message. The method and system of the invention can be quickly prototyped and implemented to various systems due to its simplicity.Type: ApplicationFiled: April 3, 2008Publication date: October 9, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shen-Ming CHUNG, Jun-Yao WANG, Hsiao-Hui LEE
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Publication number: 20070283041Abstract: The present invention relates to a method and system for recognizing offloaded packets. Firstly, according to the method of the present invention, a common attribute of connection identifications among a plurality of offloaded connections is calculated. Then, a connection identification of a packet is recognized to determine whether the connection identification of the packet has the common attribute so as to determine whether the packet is a non-offloaded packet. Therefore, the method of the present invention can promptly recognize the non-offloaded packet to greatly lower the recognition workload of an embedded processor, to improve the efficiency of executing a partial offloaded process by the embedded processor and to decrease the operation delay of the non-offloaded packet in a protocol offload processing system.Type: ApplicationFiled: December 27, 2006Publication date: December 6, 2007Inventors: Shen-Ming Chung, Jun-Yao Wang, Hsiao-Hui Lee
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Publication number: 20070271431Abstract: A snapshot mechanism and a method thereof used in a data processing system are provided to backup snapshot data. The snapshot mechanism includes a snapshot storage unit and a buffer storage unit, wherein the snapshot storage unit is used as a unit for storing data generated after a target storage unit snapshots data and accordingly generating a plurality of snapshot management data. In addition, the buffer storage unit temporarily stores new data and flushes the data to the target storage unit in predetermined time interval. According to the snapshot management data, the target storage unit can be rolled back or rolled forward to the status before a predetermined time.Type: ApplicationFiled: December 6, 2006Publication date: November 22, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Shyang Hwang, Ching-Hung Lin, Jun-Yao Wang, Chin-Pei Su, Tsung-Lin Tsai
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Publication number: 20070156985Abstract: A snapshot mechanism of a data processing system is provided herein. The snapshot mechanism includes providing a snapshot storage unit for storing the data created when snapshotting the target storage units and generating a plurality of snapshot images accordingly. Two different types of address tables in the snapshot image are used for corresponding to the storage units of the snapshot storage unit and the target storage units. The status of the target storage units can be recovered to the status at a predetermined time ago according to the snapshot images. The two types of address tables are respectively used for storing the data created by the data processing system and history data so as to prevent the data stored in the target storage units to be overwritten.Type: ApplicationFiled: August 10, 2006Publication date: July 5, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Lin Tsai, Jun-Yao Wang, Shou-Jen Wey
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Publication number: 20070143513Abstract: The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, and an interrupt controller. The first calculating device is used for calculating packet information of a plurality of packets. The packet header parser is used for recognizing the type of service field in each packet and for generating a minimum delay control signal. The second calculating device is used for determining a coalescing interrupt number signal according to the packet information and the minimum delay control signal. The interrupt controller is used for transmitting an interrupt control signal to process the packet according to the coalescing interrupt number signal.Type: ApplicationFiled: July 18, 2006Publication date: June 21, 2007Inventors: Wen-Fong Wang, Jun-Yao Wang
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Patent number: 7174374Abstract: The present invention discloses a multi-priority media access control method for a multi-channel slotted ring network. In the slotted ring networks, each node has one tunable transmitter and one fixed receiver for data channels, and is able to inspect slot status on all channels. The header slot format defines the slot priorities on ring networks and limits which packets can be transmitted through the slots. By assigning slot priority based on two thresholds to raise and lower slot priority, multiple priority packets can be transmitted.Type: GrantFiled: May 13, 2002Date of Patent: February 6, 2007Assignee: Industrial Technology Research InstituteInventors: Jun-Yao Wang, Wen-Shyang Hwang, Wen-Fong Wang, Ce-Kuen Shieh
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Publication number: 20050281286Abstract: A storage structure and method having multiple protocol processor units are disclosed. The storage structure comprises a host CPU, a main memory, a storage device, a switch fabric, and a host bus adapter module. The host bus adapter module includes a plurality of protocol processor nodes for processing frames received from a network, and storing those frames into the storage device. A processing module of the host bus adapter module extracts the session information of each frame and compares it with entries recorded in a look-up table. If the connection information hits one entry of the look-up table, the frame can be bypassed into a corresponding protocol processor node according to the definition of the look-up table. Otherwise, a new entry will be inserted into the look-up table for designating a corresponding protocol processor node.Type: ApplicationFiled: November 3, 2004Publication date: December 22, 2005Applicant: Industrial Technology Research InstituteInventors: Jun-Yao Wang, Chung-Ho Chen, Chao-Lin Su, Chao-Hsien Hsu, Cheng-Yeh Yu, I-Cheng Chung
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Publication number: 20030212812Abstract: The present invention discloses a multi-priority media access control method for a multi-channel slotted ring network. In the slotted ring networks, each node has one tunable transmitter and one fixed receiver for data channels, and is able to inspect slot status on all channels. The header slot format defines the slot priorities on ring networks and limits which packets can be transmitted through the slots. By assigning slot priority based on two thresholds to raise and lower slot priority, multiple priority packets can be transmitted.Type: ApplicationFiled: May 13, 2002Publication date: November 13, 2003Applicant: Industrial Technology Research InstituteInventors: Jun-Yao Wang, Wen-Shyang Hwang, Wen-Fong Wang, Ce-Kuen Shieh