Patents by Inventor Jun-Yean Chiou

Jun-Yean Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9658278
    Abstract: A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Po-Ju Chiu, Jun Yean Chiou, Chao-Jen Cheng
  • Publication number: 20150212146
    Abstract: A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hao LIAO, Chu Fu CHEN, Po-Ju CHIU, Jun Yean CHIOU, Chao-Jen CHENG
  • Patent number: 6890772
    Abstract: A method of forming a SIMS monitor device for determining a doping profile of a semiconductor device structure including providing a plurality of regularly repeating semiconductor structures including a doping profile to form a monitor device including at least one layer of the regularly repeating semiconductor structures; planarizing the monitor device through a thickness of the regularly repeating semiconductor structures to reveal a target surface overlying the doping profile to form a monitor pattern; and, sputtering the target surface over a sputtering area including the monitor pattern through a thickness thereof while simultaneously detecting and counting over a time interval at least one type of species ejected from the target surface according to a secondary ion mass spectroscopy procedure (SIMS).
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: May 10, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chin-Kai Liu, Jun-Yean Chiou, Pei-Fen Chou, Han-Shun Lui
  • Publication number: 20030127601
    Abstract: A method of forming a SIMS monitor device for determining a doping profile of a semiconductor device structure including providing a plurality of regularly repeating semiconductor structures including a doping profile to form a monitor device including at least one layer of the regularly repeating semiconductor structures; planarizing the monitor device through a thickness of the regularly repeating semiconductor structures to reveal a target surface overlying the doping profile to form a monitor pattern; and, sputtering the target surface over a sputtering area including the monitor pattern through a thickness thereof while simultaneously detecting and counting over a time interval at least one type of species ejected from the target surface according to a secondary ion mass spectroscopy procedure (SIMS).
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Kai Liu, Jun-Yean Chiou, Pei-Fen Chou, Han-Shun Lui