Patents by Inventor Jun Yeon WON

Jun Yeon WON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085469
    Abstract: A transmitting and receiving circuit may include a first CMOS inverter configured to receive a first power supply signal and a first input signal. The transmitting and receiving circuit may include a first calculation amplifier including a non-inverted input terminal connected to an output terminal of the first CMOS inverter, and a first resistor connected between the output terminal of the first calculation amplifier and a first node. The output terminal of the first calculation amplifier and an inverted input terminal of the first calculation amplifier may be connected to each other. A first output signal may have a level smaller than that of the first input signal and may be output to the first node.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 14, 2024
    Inventors: Seong Kwan LEE, Min Ho KANG, Hyung-Sun RYU, Cheol Min PARK, Jun Yeon WON, Jae Moo CHOI
  • Patent number: 9891594
    Abstract: A delay line-based time to digital converter includes: a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected; a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; and a timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 13, 2018
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae Sung Lee, Jun Yeon Won
  • Publication number: 20180017944
    Abstract: A delay line-based time to digital converter includes: a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected; a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; and a timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value.
    Type: Application
    Filed: August 26, 2015
    Publication date: January 18, 2018
    Inventors: Jae Sung LEE, Jun Yeon WON