Abstract: A method of forming a contact structure in a semiconductor device includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole. The pad contact hole is filled with a conductive pad. Thermal oxidation annealing is then carried out to form an oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.

Abstract: A method of forming a contact structure in a semiconductor device includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole. The pad contact hole is filled with a conductive pad. Thermal oxidation annealing is then carried out to form an oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.

Abstract: There is provided a method for manufacturing a semiconductor device which can provide global planarization between a cell array region and a periphery region by a simple process. An interlevel dielectric layer is formed over the entire surface of a semiconductor substrate where a global step difference exists between a cell array region and a periphery region. A first material layer serving as a stopper is formed on the interlevel dielectric layer. A contact hole partially exposing the semiconductor substrate of the cell array region is formed by patterning the first material layer and the interlevel dielectric layer. A conductive layer is formed over the entire surface of the semiconductor substrate where the contact hole is formed. Global planarization is provided between the cell array region and the periphery region by performing a chemical mechanical polishing (CMP) process on the semiconductor substrate where the conductive layer is formed.

Abstract: A semiconductor memory device with a capacitor-over-bitline (COB) structure and a method for fabricating the same. The semiconductor memory device includes a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode, a first interlayer insulating layer formed over the substrate including the transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate including the bitline, for insulating the bitline from a storage node of a capacitor. A surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline.

Abstract: A semiconductor memory device with a capacitor-over-bitline (COB) structure and a method for fabricating the same. The semiconductor memory device includes a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode, a first interlayer insulating layer formed over the substrate including the transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate including the bitline, for insulating the bitline from a storage node of a capacitor. A surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline.