Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.

Abstract: A method for manufacturing a semiconductor device capacitor includes the steps of forming a first conductive layer on a semiconductor substrate, forming a storage node pattern on the first conductive layer, forming first conductive sidewalls on the side surfaces of the storage node pattern, removing the storage node pattern, forming material sidewalls on the side surfaces of the conductive sidewalls, forming second conductive sidewalls on the side surfaces of the material sidewalls, and removing the material sidewalls. Thus, a process simplification is achieved and capacitance is increased easily so that a high-integration memory cell can be ensured.