Patents by Inventor Jun-Youn Kim

Jun-Youn Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939334
    Abstract: The present disclosure relates to a novel PLK1 degradation inducing compound having a structure according to Formula I, a method for preparing the same, and the use thereof. The compounds of the present disclosure exhibit an effect of inducing PLK1 degradation. Therefore, the compounds of the present disclosure may be effectively utilized for preventing or treating PLK1-related diseases.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 26, 2024
    Assignee: UPPTHERA, INC.
    Inventors: Soo Hee Ryu, Im Suk Min, Han Kyu Lee, Seong Hoon Kim, Hye Guk Ryu, Keum Young Kang, Sang Youn Kim, So Hyun Chung, Jun Kyu Lee, Gibbeum Lee
  • Patent number: 11912710
    Abstract: The present disclosure relates to a novel PLK1 degradation inducing compound having a structure according to Formula I, a method for preparing the same, and the use thereof. The compounds of the present disclosure exhibit an effect of inducing PLK1 degradation. Therefore, the compounds of the present disclosure may be effectively utilized for preventing or treating PLK1-related diseases.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 27, 2024
    Assignee: UPPTHERA, INC.
    Inventors: Soo Hee Ryu, Im Suk Min, Han Kyu Lee, Seong Hoon Kim, Hye Guk Ryu, Keum Young Kang, Sang Youn Kim, So Hyun Chung, Jun Kyu Lee, Gibbeum Lee
  • Publication number: 20240038927
    Abstract: A colour conversion resonator system, comprising: a first partially reflective region configured to transmit light of a first primary peak wavelength and to reflect light of a second primary peak wavelength; a second partially reflective region configured to at least partially transmit light of the first and second primary peak wavelengths and to reflect light of a third primary peak wavelength; a third partially reflective region configured to at least partially reflect light with the third primary peak wavelength; a first colour conversion resonator cavity arranged to receive input light with the first primary peak wavelength through the first partially reflective region and to convert at least some of the light of the first primary peak wavelength to provide light of the second primary peak wavelength, wherein the first colour conversion resonator cavity is arranged such that the second primary peak wavelength resonates in the first colour conversion resonator cavity and resonant light with the second prim
    Type: Application
    Filed: October 10, 2022
    Publication date: February 1, 2024
    Inventors: Jun-Youn Kim, Anwer Saeed, Andrea Pinos, Mohsin Aziz, Ian Murray, Abdul Shakoor
  • Publication number: 20230369549
    Abstract: A colour conversion resonator system, comprising: a partially reflective region configured to transmit light of a first primary peak wavelength and to reflect light of a second primary peak wavelength; a further partially reflective region configured to at least partially reflect light with the second primary peak wavelength; and a colour conversion resonator cavity comprising at least one quantum well, wherein the colour conversion resonator cavity is arranged to: receive input light with the first primary peak wavelength through the partially reflective region; and convert, by the at least one quantum well, at least some of the received input light to provide light of the second primary peak wavelength such that light of the second primary peak wavelength resonates in the cavity and light with the resonant second primary peak wavelength is output through the further partially reflective region, wherein the at least one quantum well is placed to coincide with an antinode of the colour conversion resonator ca
    Type: Application
    Filed: October 22, 2021
    Publication date: November 16, 2023
    Inventors: Jun-Youn Kim, Anwer Saeed, Andrea Pinos, Mohsin Aziz, Ian Murray, Abdul Shakoor
  • Publication number: 20230299119
    Abstract: According to the first aspect of the disclosure, a method of forming a light emitting device array precursor is provided. The method comprises forming a first light emitting layer on a first substrate, forming an array of first light emitting devices from the first light emitting layer, each first light emitting device configured to emit light having a first wavelength. A first bonding layer is formed on the first light emitting layer. A second light emitting layer is formed on a second substrate, the second light emitting layer configured to emit light having a second wavelength different to the first wavelength. A second bonding layer is formed on the second light emitting layer. The second bonding layer is bonded to a handling substrate, followed by removing the second substrate from the second light emitting layer. A third bonding layer is formed on the second light emitting layer on an opposite side of the second light emitting layer to the handling layer.
    Type: Application
    Filed: June 23, 2021
    Publication date: September 21, 2023
    Applicant: Plessey Semiconductors Limited
    Inventors: Mohsin AZIZ, Jun-Youn KIM, Abdul SHAKOOR, James CARSWELL, Anwer SAEED, Kevin STRIBLEY
  • Publication number: 20230238479
    Abstract: A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial cr
    Type: Application
    Filed: July 14, 2021
    Publication date: July 27, 2023
    Inventors: Andrea Pinos, WeiSin Tan, Samir Mezouari, John Lyle Whiteman, Xiang Yu, Jun-Youn Kim
  • Publication number: 20230238421
    Abstract: A method of manufacturing a LED precursor and a LED precursor is provided. The LED precursor is manufactured by forming a monolithic growth stack having a growth surface and forming a monolithic LED stack on the growth surface. The monolithic growth stack comprises a first semiconducting layer comprising a Group III-nitride, a second semiconducting layer, and third semi-conducting layer. The second semiconducting layer comprises a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×1018 cm-3. The second semiconducting layer has an areal porosity of at least 15% and a first in-plane lattice constant. The third semiconducting layer comprises a second Group III-nitride different to the first Group-III-nitride.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 27, 2023
    Applicant: PLESSEY SEMICONDUCTORS LIMITED
    Inventors: Andrea PINOS, Wei Sin TAN, Jun Youn KIM, Xiang YU, Simon ASHTON, Samir MEZOUARI
  • Publication number: 20230139307
    Abstract: A micro-light emitting diode includes a substrate including at least a first portion of an n-type semiconductor layer, and a mesa structure on the substrate and characterized by a linear lateral dimension equal to or less than about 3 ?m. The mesa structure includes a plurality of epitaxial layers, and a conductive distributed Bragg reflector (DBR) on the plurality of epitaxial layers. The conductive DBR includes a plurality of transparent conductive oxide layers and covers between about 80% and about 100% of a full lateral area of the plurality of epitaxial layers. The micro-LED also includes a dielectric layer on sidewalls of the mesa structure, a reflective metal layer on sidewalls of the dielectric layer and electrically coupled to the first portion of the n-type semiconductor layer, and a first metal electrode in direct contact with the conductive DBR.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Abdul SHAKOOR, Mohsin AZIZ, Jun-Youn KIM
  • Publication number: 20230119031
    Abstract: A light emitting diode structure comprising: a p-type region; an n-type region; a light emitting region for recombination of carriers injectable by the p-type region and the n-type region; and a via passing through the light emitting region, wherein the via defines the perimeter of a light emitting surface of at least one pixel and comprises a material configured to enable injection of carriers into the p-type region or the n-type region, wherein one of the p-type region and n-type region is configured such that carriers generated in the one of the p-type region and the n-type region diffuses through the other one of the n-type region and the p-type region prior to recombination in the light emitting region.
    Type: Application
    Filed: March 15, 2021
    Publication date: April 20, 2023
    Inventors: Andrea Pinos, Jun-Youn Kim, Samir Mezouari, WeiSin Tan
  • Patent number: 11569414
    Abstract: A micro-light emitting diode includes a substrate including at least a first portion of an n-type semiconductor layer, and a mesa structure on the substrate and characterized by a linear lateral dimension equal to or less than about 3 ?m. The mesa structure includes a plurality of epitaxial layers, and a conductive distributed Bragg reflector (DBR) on the plurality of epitaxial layers. The conductive DBR includes a plurality of transparent conductive oxide layers and covers between about 80% and about 100% of a full lateral area of the plurality of epitaxial layers. The micro-LED also includes a dielectric layer on sidewalls of the mesa structure, a reflective metal layer on sidewalls of the dielectric layer and electrically coupled to the first portion of the n-type semiconductor layer, and a first metal electrode in direct contact with the conductive DBR.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 31, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Abdul Shakoor, Mohsin Aziz, Jun-Youn Kim
  • Patent number: 11508890
    Abstract: A display device includes a plurality of light emitting diodes (LEDs) having walls that extend through a transparent semiconductor layer and beyond the surface of the transparent semiconductor layer. Each of the walls surrounds at least part of each of the plurality of LEDs to collimate the light emitted by the plurality of LEDs. In some embodiments, the walls collimate the light emitted by the LEDs by reflecting the light or absorbing a portion of the light. The display device may further include an array of optical lenses that faces the surface of the transparent semiconductor layer to further collimate the light emitted from the LEDs.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 22, 2022
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Mohsin Aziz, Jun-Youn Kim, Samir Mezouari, Abdul Shakoor, James Walker Carswell
  • Publication number: 20220310891
    Abstract: A display device includes a plurality of light emitting diodes (LEDs) having walls that extend through a transparent semiconductor layer and beyond the surface of the transparent semiconductor layer. Each of the walls surrounds at least part of each of the plurality of LEDs to collimate the light emitted by the plurality of LEDs. In some embodiments, the walls collimate the light emitted by the LEDs by reflecting the light or absorbing a portion of the light. The display device may further include an array of optical lenses that faces the surface of the transparent semiconductor layer to further collimate the light emitted from the LEDs.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Mohsin Aziz, Jun-Youn Kim, Samir Mezouari, Abdul Shakoor, James Walker Carswell
  • Publication number: 20220271193
    Abstract: A light emitting diode is provided having a LED layer configured to emit pump light having a pump light wavelength from a light emitting surface, the LED layer comprising a plurality of Group III-nitride layers. A container layer is provided on the light emitting surface of the LED layer, the container surface including an opening defining a container volume through the container layer to the light emitting surface of the LED layer. A colour converting layer is provided in the container volume, the colour converting Got layer configured to absorb pump light and emit converted light of a converted light wavelength longer than the pump light wavelength. A lens is provided on the container surface over the opening, the lens having a convex surface on an opposite side of the lens to the colour converting layer. A pump light reflector laminate provided over the convex surface of the lens the pump light reflector laminate having a stop-band configured to reflect the pump light centred on a first wavelength.
    Type: Application
    Filed: July 24, 2020
    Publication date: August 25, 2022
    Applicant: PLESSEY SEMICONDUCTORS LIMITED
    Inventors: Jun-Youn KIM, Samir MEZOUARI, John SHANNON, Kevin STRIBLEY, Mohsin AZIZ
  • Publication number: 20220262981
    Abstract: A micro-light emitting diode includes a substrate including at least a first portion of an n-type semiconductor layer, and a mesa structure on the substrate and characterized by a linear lateral dimension equal to or less than about 3 ?m. The mesa structure includes a plurality of epitaxial layers, and a conductive distributed Bragg reflector (DBR) on the plurality of epitaxial layers. The conductive DBR includes a plurality of transparent conductive oxide layers and covers between about 80% and about 100% of a full lateral area of the plurality of epitaxial layers. The micro-LED also includes a dielectric layer on sidewalls of the mesa structure, a reflective metal layer on sidewalls of the dielectric layer and electrically coupled to the first portion of the n-type semiconductor layer, and a first metal electrode in direct contact with the conductive DBR.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Inventors: Abdul SHAKOOR, Mohsin AZIZ, Jun-Youn KIM
  • Publication number: 20220231081
    Abstract: A light emitting diode (LED) precursor is provided. The LED precursor comprises a substrate (10), an LED structure (30) comprising a plurality of Group III-nitride layers, and a passivation layer (40). The LED structure comprises a p-type semiconductor layer (36), an n-type semiconductor layer (32), and an active layer (34) between the p-type and n-type semiconductor layers. Each of the plurality of Group III-nitride layers comprises a crystalline Group III-nitride. The LED structure has a sidewall (37) which extends in a plane orthogonal to a (0001) crystal plane of the Group III-nitride layers. The passivation layer is provided on the sidewall of the LED structure such that the passivation layer covers the active layer. The passivation layer comprises a crystalline Group III-nitride with a bandgap higher than a bandgap of the active layer.
    Type: Application
    Filed: May 19, 2020
    Publication date: July 21, 2022
    Applicant: PLESSEY SEMICONDUCTORS LIMITED
    Inventors: Jun-Youn KIM, Mohsin AZIZ, John SHANNON, Kevin STRIBLEY, Ian DANIELS
  • Patent number: 10900142
    Abstract: An apparatus includes a deposition chamber housing that accommodates a growth substrate, a supply nozzle to supply a deposition gas for forming a target large-size substrate on the growth substrate into the deposition chamber housing, a susceptor to support the growth substrate and expose a rear surface of the growth substrate to an etch gas, and an inner liner connected to the susceptor. The inner liner is to isolate the etch gas from the deposition gas and guide the etch gas toward the rear surface of the growth substrate. The susceptor includes a center hole that exposes the rear surface of the growth substrate and a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sam-mook Kang, Jun-youn Kim, Young-jo Tak, Mi-hyun Kim, Young-soo Park
  • Patent number: 10600645
    Abstract: A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi Hyun Kim, Sam Mook Kang, Jun Youn Kim, Young Jo Tak
  • Patent number: 10338876
    Abstract: A multivision apparatus may include a display panel that includes a display screen including a first region and an adjacent second region. The first region may include first pixels, and the second region may include second pixels. The first pixels and the second pixels have different structures. The display panel may display a single image across the first region and the second region of the display screen. The multivision apparatus may include an array of interconnected display panels configured to collectively display an image, based on each given display panel displaying a separate sub-image in the first and second regions of the given display panel.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Youn Kim, Hyun Seong Kum, Young Hwan Park
  • Patent number: 10094045
    Abstract: In a method of manufacturing a GaN substrate, a capping layer may be formed on a first surface of a silicon substrate. A buffer layer may be formed on a second surface of the silicon substrate. The second surface may be opposite the first surface. A GaN substrate may be formed on the buffer layer by performing a hydride vapor phase epitaxy (HVPE) process. The capping layer and the silicon substrate may be removed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Hyun Kim, Sam-Mook Kang, Jun-Youn Kim, Young-Jo Tak, Young-Soo Park
  • Publication number: 20180174823
    Abstract: A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.
    Type: Application
    Filed: July 28, 2017
    Publication date: June 21, 2018
    Inventors: Mi Hyun KIM, Sam Mook KANG, Jun Youn KIM, Young Jo TAK