Patents by Inventor Jun-Young Go

Jun-Young Go has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BGA package with stacked semiconductor chips and method of manufacturing the same
    Patent number: 7528475
    Abstract: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 5, 2009
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jun-Young Go, Byung-Seok Jun, Jae-Hong Kim
  • BGA package with stacked semiconductor chips and method of manufacturing the same
    Patent number: 7262080
    Abstract: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 28, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Young Go, Byung-Seok Jun, Jae-Hong Kim
  • BGA package with stacked semiconductor chips and method of manufacturing the same
    Publication number: 20070063332
    Abstract: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.
    Type: Application
    Filed: November 22, 2006
    Publication date: March 22, 2007
    Inventors: Jun-Young Go, Byung-Seok Jun, Jae-Hong Kim
  • BGA package with stacked semiconductor chips and method of manufacturing the same
    Publication number: 20050012195
    Abstract: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.
    Type: Application
    Filed: May 21, 2004
    Publication date: January 20, 2005
    Inventors: Jun-Young Go, Byung-Seok Jun, Jae-Hong Kim