Patents by Inventor Jun Zhai

Jun Zhai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105545
    Abstract: Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Publication number: 20240105702
    Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.
    Type: Application
    Filed: March 6, 2023
    Publication date: March 28, 2024
    Inventors: Chonghua Zhong, Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Publication number: 20240105626
    Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.
    Type: Application
    Filed: April 6, 2023
    Publication date: March 28, 2024
    Inventors: Sanjay Dabral, Jun Zhai, Kunzhong Hu, SivaChandra Jangam, Zhitao Cao
  • Publication number: 20240105704
    Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 28, 2024
    Inventors: Chonghua Zhong, Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Publication number: 20240088032
    Abstract: Microelectronic modules are described. In an embodiment, a microelectronic module includes a module substrate, a chip mounted onto the module substrate, and a semiconductor-based integrated passive device between the chip and the module substrate. The semiconductor-based integrated passive device may include an upper RDL stack-up with thicker wiring layers than a lower BEOL stack-up. The semiconductor-based integrated passive device may be further solder bonded or hybrid bonded with the chip.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Vidhya Ramachandran, Chi Nung Ni, Chueh-An Hsieh, Rekha Govindaraj, Jun Zhai, Long Huang, Rohan U. Mandrekar, Saumya K. Gandhi, Zhuo Yan, Yizhang Yang, Saurabh P. Sinha, Antonietta Oliva
  • Publication number: 20240081352
    Abstract: The present disclosure provides a blending method of high-quality and dual-purpose flour for bread and noodles, belonging to the technical field of flour processing. The method includes: selecting flour of a high-quality and dual-purpose wheat variety for bread and noodles as a high-quality basic flour for blending; according to a large gradient experimental design, selecting a gradient range ratio with a sedimentation value ?46.0 mL and a dough development time ?9.6 min, followed by subdividing for small gradient experiments; selecting a ratio with flour sedimentation value and dough development time that reach an ideal value to blend a large amount of flour; and making bread and noodles for scoring, followed by determining a blending ratio if a scoring result reaches an ideal value.
    Type: Application
    Filed: September 11, 2022
    Publication date: March 14, 2024
    Inventors: Yan Zi, Jianmin Song, Xiao Ma, Aifeng Liu, Wei Ju, Haosheng Li, Dungong Cheng, Canguo Wang, Jun Guo, Jianjun Liu, Xinyou Cao, Cheng Liu, Shengnan Zhai, Faji Li, Ran Han, Zhendong Zhao
  • Patent number: 11908819
    Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Apple Inc.
    Inventors: Jun Chung Hsu, Chih-Ming Chung, Jun Zhai, Yifan Kao, Young Doo Jeon, Taegui Kim
  • Publication number: 20240047353
    Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Sanjay Dabral, Jun Zhai, Jung-Cheng Yeh, Kunzhong Hu, Raymundo Camenforte, Thomas Hoffmann
  • Publication number: 20240038689
    Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Jun Zhai, Kunzhong Hu
  • Publication number: 20240030472
    Abstract: A membrane electrode assembly (MEA) includes a membrane, a cathode catalyst layer, a cathode co-catalyst layer including a hydrogen reservoir, an anode catalyst layer, and an anode co-catalyst layer including a hydrogen reservoir. The anode co-catalyst layer and the cathode co-catalyst layer cap a cathode potential at lower than 1.5V and an anode potential at lower than 1.0V. The anode co-catalyst layer and the cathode co-catalyst layer can include a platinum doped rare earth oxide, such as platinum doped cerium oxide.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 25, 2024
    Inventors: Rajesh Bashyam, Jun Zhai
  • Publication number: 20240014178
    Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 11, 2024
    Inventors: Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran
  • Patent number: 11862557
    Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Jun Zhai, Jung-Cheng Yeh, Kunzhong Hu, Raymundo Camenforte, Thomas Hoffmann
  • Publication number: 20230402373
    Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 14, 2023
    Inventors: Sanjay Dabral, Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte
  • Patent number: 11824015
    Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Jun Zhai, Kunzhong Hu
  • Publication number: 20230335494
    Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Inventors: Sanjay Dabral, Zhitao Cao, Kunzhong Hu, Jun Zhai
  • Publication number: 20230335440
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 19, 2023
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Publication number: 20230317708
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 5, 2023
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Publication number: 20230317624
    Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.
    Type: Application
    Filed: November 28, 2022
    Publication date: October 5, 2023
    Inventors: Wei Chen, Yi Xu, Jie-Hua Zhao, Jun Zhai
  • Publication number: 20230299668
    Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Inventors: Sanjay Dabral, David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao
  • Publication number: 20230279556
    Abstract: Disclosed are an electrolysis cell system and a method for preparing hydrogen and oxygen. The electrolysis cell system includes: an anode chamber with an inlet and an outlet; a cathode chamber with an inlet and an outlet; a composite membrane electrode set between the anode chamber and the cathode chamber, which includes a cation exchange membrane in alkali-ion form with an anode catalyst coated on one side thereof and a cathode catalyst coated on the other side thereof; a continuous or intermittent flow of an aqueous alkaline electrolyte through the anode chamber and the cathode chamber. The electrolysis cell system of the present disclosure features low material cost, long membrane service life, high operating temperature, low operating requirements and high safety; when it is used to prepare hydrogen and oxygen, gas with relatively high purity can be obtained.
    Type: Application
    Filed: September 30, 2022
    Publication date: September 7, 2023
    Inventors: Arthur Ernest Koschany, Liqin Zhou, Jun Zhai