Abstract: Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

Abstract: Integrated circuit (IC) structures methods of assembling an integrated circuit structure are described in which various etching sequences including plasma etching are utilized to remove direct bonded interfaces at die corners or edges that are at high-risk for non-bonding or delamination. In an embodiment, a laser etching operation is first performed to remove molding compound at local areas between adjacent components, following by a plasma dicing operation through the direct bonded structures.

Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

Abstract: Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

Abstract: Electronic packages and package-on-package structures are described. In an embodiment, an electronic package include multiple staircased dies and multiple vertical wire bonds encapsulated by a molding layer, where the multiple vertical wire bonds protrude from a top surface of the molding layer so that the vertical wire bonds stand proud above a top surface of the molding layer.

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Abstract: Memory systems and methods of assembly are described in which a memory system includes a routing substrate, a processor on a first side of the routing substrate, a memory die stack on the first side of the routing substrate, and a buffer bridge die embedded in the routing substrate and electrically connecting the memory die stack with the processor.

Abstract: Packages with wafer level land grid arrays are described. In an embodiment, a package includes a die and a package routing layer over the die, where the package routing layer includes a first land that spans over a first set of vias, and a second land that spans over a second set of vias, where the vias may be connected to a metal redistribution line or directly connected to die contact pad of the die.

Abstract: Electronic packages and methods of fabrication are described. In an embodiment, an electronic package includes a die stack of a plurality of vertically stacked dies, a first interposer laterally adjacent to the die stack, a first plurality of bond wires electrically connecting a first group of the plurality of vertically stacked dies to the interposer, and a molding compound layer encapsulating the die stack, the interposer, and the plurality of first plurality of bond wires.

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.

Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.