Patents by Inventor Jun Zhan

Jun Zhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250132284
    Abstract: Embodiments of the present disclosure provide a bond stage for bonding a semiconductor integrated circuit (IC) die. The bond stage includes a bonding platform having a top surface and a bottom surface opposing the top surface, a first actuator operable to tilt the bonding platform about a first rotation axis, and a plurality of contact sensors disposed at the bonding platform.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Inventors: Amram EITAN, Hui-Ting LIN, Chih-Yuan CHIU, Kai Jun ZHAN, Yi Chen WU
  • Patent number: 12273152
    Abstract: An obstacle recognition method and apparatus, and a related device are provided. The method includes: obtaining an actual path loss value between a first AP and a second AP, path loss value pairs between a terminal and a plurality of AP pairs, and path loss values of the plurality of AP pairs; obtaining, based on the path loss value pairs between the terminal and the plurality of AP pairs, an AP pair similar to an AP pair formed by the first AP and the second AP; obtaining a second path loss value between the first AP and the second AP based on a path loss value of the similar AP pair; and comparing the second path loss value between the first AP and the second AP with the actual path loss value, to determine whether an obstacle exists between the first AP and the second AP.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 8, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haiyang He, Xiaofei Bai, Jun Zhan, Dong Yang, Qikun Wei
  • Publication number: 20240404988
    Abstract: A bonded assembly may be formed by providing at least a first packaging substrate in a low-oxygen ambient; providing at least a first semiconductor package in the low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient by directing at least one first plasma jet to first solder material portions bonded to the first semiconductor package; and bringing the first solder material portions onto, or in proximity to, first substrate-side bonding structures located on the first packaging substrate while the at least one first plasma jet is directed to the first solder material portions. The first substrate-side bonding structures are treated with the first plasma jet. The first semiconductor package is bonded to the first packaging substrate while, or after, the first substrate-side bonding structures are treated with the first plasma jet.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Ming-Da Cheng, Chih-Yuan Chiu, Amram Eitan
  • Publication number: 20240404989
    Abstract: A bonded assembly may be formed by providing a wafer comprising at least a first packaging substrate and a second packaging substrate in a low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient while performing a first substrate-treatment process on the first packaging substrate in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; and performing a second plasma package-treatment process on the second semiconductor package while performing a second substrate-treatment process on the second packaging substrate and while bonding the first semiconductor package to the first packaging substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Chih-Yuan Chiu, Ming-Da Cheng, Amram Eitan
  • Publication number: 20240396696
    Abstract: A dynamic channel allocation system and a network device are disclosed. The method includes: After obtaining signal interference distribution between a plurality of APs and an occlusion relationship between the plurality of APs, a radio controller allocates channels to the plurality of APs based on the signal interference distribution and the occlusion relationship, where channels allocated to APs that have an occlusion relationship are different. In this application, after obtaining the occlusion relationship between the plurality of APs, the radio controller allocates, during channel allocation to the plurality of APs, different channels to APs that have an occlusion relationship, so that co-channel interference caused by the case in which a same channel is allocated to an occluded AP pair is avoided, and communication quality of a wireless network is improved.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Zhan, Zhenwen Zhu
  • Publication number: 20240332235
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Patent number: 12072774
    Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to store a first set of data comprising an operating system in a first location; store a second set of data comprising application data in a second location; expose the first and second sets of data in a combined union mount filesystem; and create a backup of the second set of data, but not the first set of data, by creating a copy of the second location.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: August 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Alice Min Li, Jun Zhan, Kai Chen
  • Publication number: 20240258259
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Publication number: 20240258266
    Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 1, 2024
    Inventors: Kai Jun Zhan, Chin-Fu Kao, Kuang-Chun Lee, Ming-Da Cheng, Chen-Shien Chen
  • Publication number: 20240231803
    Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to perform a maintenance operation involving a plurality of hosts of an information handling system cluster by: determining a score for each host based on a sum of working memory sizes for all active virtual machines executing on such host plus a sum of persistent storage sizes for all virtual machines stored on such host; based on the determined scores, selecting a first host for upgrading; migrating at least a portion of all virtual machines stored on the first host from the first host to one or more other hosts; and causing the first host to perform the maintenance operation.
    Type: Application
    Filed: October 21, 2022
    Publication date: July 11, 2024
    Applicant: Dell Products L.P.
    Inventors: Kai CHEN, Jun ZHAN, Stéphane MENG, HongGang LIU, Yuyan CHEN, Carl SHI, Michael G. VARTERESIAN
  • Publication number: 20240222312
    Abstract: A method for forming a package structure is provided. The method includes transporting a first package component into a processing chamber. The method includes positioning the first package component on a chuck table. The method includes using the chuck table to heat the first package component. The method includes holding a second package component with a bonding head. The bonding head communicates with a plurality of vacuum devices via a plurality of vacuum tubes, and the vacuum devices each operate independently. The method also includes bonding the first package component and the second package component in the processing chamber to form the package structure.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 4, 2024
    Inventors: Kai Jun ZHAN, Chang-Jung HSUEH, Hui-Min HUANG, Wei-Hung LIN, Ming-Da CHENG
  • Patent number: 12015002
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Publication number: 20240194633
    Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.
    Type: Application
    Filed: March 23, 2023
    Publication date: June 13, 2024
    Inventors: Amram Eitan, Hui-Ting Lin, Chien-Hung Chen, Chih-Yuan Chiu, Kai Jun Zhan
  • Patent number: 11990440
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Patent number: 11978720
    Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai Jun Zhan, Chin-Fu Kao, Kuang-Chun Lee, Ming-Da Cheng, Chen-Shien Chen
  • Publication number: 20240134632
    Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to perform a maintenance operation involving a plurality of hosts of an information handling system cluster by: determining a score for each host based on a sum of working memory sizes for all active virtual machines executing on such host plus a sum of persistent storage sizes for all virtual machines stored on such host; based on the determined scores, selecting a first host for upgrading; migrating at least a portion of all virtual machines stored on the first host from the first host to one or more other hosts; and causing the first host to perform the maintenance operation.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Applicant: Dell Products L.P.
    Inventors: Kai CHEN, Jun ZHAN, Stéphane MENG, HongGang LIU, Yuyan CHEN, Carl SHI, Michael G. VARTERESIAN
  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
  • Patent number: 11961817
    Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai Jun Zhan, Chang-Jung Hsueh, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 11942445
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240095128
    Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to store a first set of data comprising an operating system in a first location; store a second set of data comprising application data in a second location; expose the first and second sets of data in a combined union mount filesystem; and create a backup of the second set of data, but not the first set of data, by creating a copy of the second location.
    Type: Application
    Filed: September 29, 2022
    Publication date: March 21, 2024
    Applicant: Dell Products L.P.
    Inventors: Alice Min LI, Jun ZHAN, Kai CHEN