Patents by Inventor Jun Zhuang

Jun Zhuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132120
    Abstract: A power decentralized electric locomotive apparatus includes an electric locomotive and a plurality of muck trucks. The electric locomotive and the plurality of muck trucks are connected in sequence, and a mater drive motor is fixedly mounted on the electric locomotive. A slave drive motor is fixedly mounted on at least one of the muck trucks; a torque of the slave drive motor is smaller than a torque of the mater drive motor; and the slave drive motor cooperates with the mater drive motor, to enable the muck truck to travel on rails and reduce drive power and self-weight of the electric locomotive.
    Type: Application
    Filed: November 12, 2021
    Publication date: April 25, 2024
    Applicant: China Railway Engineering Services Co., Ltd.
    Inventors: Yuanshun Zhuang, Yang Deng, Caihong Li, Yuanyuan Mei, Wenju Chen, Longguan Zhang, Kaifu Li, Rui Han, Heng Li, Chuan Li, Jun Zheng, Yang Qian, Tao Du, Xudong Gao, Yuchen Wang, Chuanying Jiang, Jie Li
  • Publication number: 20240111536
    Abstract: The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Shaoli Liu, Bingrui Wang, Xiaoyong ZHOU, Yimin ZHUANG, Huiying LAN, Jun LIANG, Hongbo ZENG
  • Publication number: 20240016517
    Abstract: Presented is a system and method for implanting a flexible electrode array in a biological organ. The system includes an electrode implant tool that includes an elongate rod and an electrode implant assembly having a plurality of attachment members. The electrode implant assembly further includes a ring member connected to each of the attachment members. A variable magnetic field generator is arranged in the ring member.
    Type: Application
    Filed: July 16, 2022
    Publication date: January 18, 2024
    Inventor: Jun Zhuang
  • Patent number: 11785897
    Abstract: A power tool is provided, which comprises a housing, a motor located within the housing, and a motion sensor. The motion sensor is adapted to control the operation of the motor in response to changes in position or angle of the power tool. The motion sensor can determine the angle between the power tool and the horizontal plane, and operation of the motor is controlled accordingly.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 17, 2023
    Assignee: TECHTRONIC POWER TOOLS TECHNOLOGY LIMITED
    Inventors: Hei Man Raymond Lee, Yong Min Li, Ming Jun Zhuang
  • Patent number: 11706141
    Abstract: In one embodiment, a method includes performing, by a router, a destination address lookup of an IP packet in a Forwarding Information Base (FIB) and identifying, by the router, an equal cost multi-path (ECMP) object from the destination address lookup. The ECMP object includes a plurality of paths for forwarding the IP packet to a destination associated with a destination address. The method further includes determining, by the router, a source interface associated with the IP packet, determining, by the router, that the source interface matches an egress interface associated with a path among the plurality of paths, and communicating, by the router, the IP packet based on the path to the destination using the egress interface.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: July 18, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Enke Chen, Jun Zhuang
  • Publication number: 20230223352
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11605597
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Publication number: 20220367369
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20220286396
    Abstract: In one embodiment, a method includes performing, by a router, a destination address lookup of an IP packet in a Forwarding Information Base (FIB) and identifying, by the router, an equal cost multi-path (ECMP) object from the destination address lookup. The ECMP object includes a plurality of paths for forwarding the IP packet to a destination associated with a destination address. The method further includes determining, by the router, a source interface associated with the IP packet, determining, by the router, that the source interface matches an egress interface associated with a path among the plurality of paths, and communicating, by the router, the IP packet based on the path to the destination using the egress interface.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Enke Chen, Jun Zhuang
  • Patent number: 11404380
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 11343188
    Abstract: In one embodiment, a method includes performing, by a router, a destination address lookup of an IP packet in a Forwarding Information Base (FIB) and identifying, by the router, an equal cost multi-path (ECMP) object from the destination address lookup. The ECMP object includes a plurality of paths for forwarding the IP packet to a destination associated with a destination address. The method further includes determining, by the router, a source interface associated with the IP packet, determining, by the router, that the source interface matches an egress interface associated with a path among the plurality of paths, and communicating, by the router, the IP packet based on the path to the destination using the egress interface.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 24, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Enke Chen, Jun Zhuang
  • Publication number: 20220102785
    Abstract: A pouch battery contains a pouch, an electrode material and a safety protection device. The electrode material is located in the pouch. The safety protection device is configured to generate an action based on a change in gas pressure within the pouch. In this way, even if the pouch battery is abnormal, its internal circuit can be cut off in time to avoid providing power to external devices while being under abnormal conditions.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Hei Man Raymond LEE, Ming Jun ZHUANG
  • Patent number: 11264818
    Abstract: A charger adapted to charge either one of a first battery pack and a second battery pack. The first battery pack and the second battery pack have respectively a first interface and a second interface being substantially different from each other. The charger includes a housing having a receiving area in which the first battery pack and the second battery pack can be selectively received in such a way that the first battery pack is accommodated in a first region and the second battery pack is accommodated in a second region. The receiving area is at least partially defined by the first region partially overlapping the second region. The charger according to the invention is adapted to charge more than one type of battery pack, which saves cost and space needed for two separate chargers.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: March 1, 2022
    Assignee: TECHTRONIC CORDLESS GP
    Inventors: Hei Man Raymond Lee, Yong Min Li, Ming Jun Zhuang
  • Patent number: 11257788
    Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 11211319
    Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Chen Yuan Weng
  • Patent number: 11201366
    Abstract: A pouch battery contains a pouch, an electrode material and a safety protection device. The electrode material is located in the pouch. The safety protection device is configured to generate an action based on a change in gas pressure within the pouch. In this way, even if the pouch battery is abnormal, its internal circuit can be cut off in time to avoid providing power to external devices while being under abnormal conditions.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 14, 2021
    Assignee: TTI (MACAO COMMERCIAL OFFSHORE) LIMITED
    Inventors: Hei Man Raymond Lee, Ming Jun Zhuang
  • Publication number: 20210327819
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11139252
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Publication number: 20210266257
    Abstract: In one embodiment, a method includes performing, by a router, a destination address lookup of an IP packet in a Forwarding Information Base (FIB) and identifying, by the router, an equal cost multi-path (ECMP) object from the destination address lookup. The ECMP object includes a plurality of paths for forwarding the IP packet to a destination associated with a destination address. The method further includes determining, by the router, a source interface associated with the IP packet, determining, by the router, that the source interface matches an egress interface associated with a path among the plurality of paths, and communicating, by the router, the IP packet based on the path to the destination using the egress interface.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Enke Chen, Jun Zhuang
  • Publication number: 20210193578
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG