Patents by Inventor Junaid Elahi

Junaid Elahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Peripheral communication system with shortcut path
    Patent number: 9875202
    Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 23, 2018
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Junaid Elahi, Joar Olai Rusten, Lasse Olsen, Lars Sundell
  • PERIPHERAL COMMUNICATION
    Publication number: 20160267038
    Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Applicant: NORDIC SEMICONDUCTOR ASA
    Inventors: Junaid Elahi, Joar Olai Rusten, Lasse Olsen, Lars Sundell
  • Programmable peripheral interconnect
    Patent number: 9087051
    Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 21, 2015
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Junaid Elahi, Joar Olai Rusten, Lasse Olsen, Lars Sundell
  • PERIPHERAL COMMUNICATION
    Publication number: 20140304439
    Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).
    Type: Application
    Filed: December 6, 2012
    Publication date: October 9, 2014
    Applicant: NORDIC SEMICONDUCTOR ASA
    Inventors: Junaid Elahi, Joar Olai Rusten, Lasse Olsen, Lars Sundell