Patents by Inventor Junan Zhang

Junan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9054681
    Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 9, 2015
    Assignee: China Electronic Technology Corporation, 24th Research Institute
    Inventors: Youhua Wang, Junan Zhang, Dongbing Fu, Gangyi Hu, Jun Liu, Ruzhang Li, Guangbing Chen
  • Publication number: 20140009399
    Abstract: The present invention discloses a keyboard, mobile phone terminal and key value output method. The keyboard comprises a keyboard bottom plate and touch keys, wherein lattices with the same size are divided in equal proportion on the keyboard bottom plate; the touch keys are embedded in each of the lattices respectively; and key values in each lattice are marked in directions adjacent to other lattices, and the touch keys are electrically connected to the keyboard bottom plate. With the technical scheme of the present invention, the number of keys and keyboard area can be reduced, areas of individual keys are increased, accuracy of the keys is improved, shortcut functions reflected by the key combinations are enriched, lifespan of the keys is increased, and comfort degree of the keys and pleasantness of the operation can be enhanced.
    Type: Application
    Filed: May 18, 2011
    Publication date: January 9, 2014
    Applicant: ZTE CORPORATION
    Inventor: Junan Zhang
  • Publication number: 20130257499
    Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.
    Type: Application
    Filed: August 23, 2011
    Publication date: October 3, 2013
    Applicant: China Electronic Technology Corporation
    Inventors: Youhua Wang, Junan Zhang, Dongbing Fu, Gangyi Hu, Jun Liu, Ruzhang Li, Guangbing Chen