Abstract: Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.