Abstract: A memory device includes a memory cell array having stacked first and second memory decks; and a peripheral circuit coupled to the memory cell array and configured to: when performing a program operation on a selected memory cell layer in the first memory deck, apply a voltage to a word line layer corresponding to the selected memory cell layer and apply a first voltage to a word line layer corresponding to an unselected memory cell layer in the first memory deck; apply a second voltage to the word line layer corresponding to the plurality of memory cell layers in the second memory deck; and apply a third voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck. The first voltage exceeds the second voltage, which exceeds the third voltage.

Abstract: The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.

Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: The present disclosure provides a method for operating a memory, a memory and a memory system, and relates to the technical field of semiconductor chip. The method includes: during the erase phase, applying an erase voltage to the word line, and applying an erase voltage to the select line coupled to a target select gate; during the program phase for select gate, applying a pass voltage to the word line, and applying a program voltage to the select line coupled to the target select gate.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: The disclosure provides a programming method of a memory, a memory and a memory system, which relate to the technical field of semiconductor chips. The programming method comprises: applying a program voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; and during a stage of applying the program voltage to the first word line, applying a turn-on voltage to a first select line and a second select line sequentially, wherein the first select line is coupled to a select transistor of the first memory cell slice, and the second select line is coupled to a select transistor of the second memory cell slice.

Abstract: Implementations of the present disclosure disclose a memory operation method, a memory device, a memory system and an electronic apparatus. The memory device includes a memory stack structure, a select stack structure on the memory stack structure, a memory string including a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure, and including a first dummy memory cell adjacent to a plug, and a plurality of memory cells, a peripheral circuit connected with the memory string and configured to program the first dummy memory cell, and apply a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of one of the plurality of memory cells close to the plug.

Abstract: The disclosure provides a three-dimensional (3D) memory, a method of fabricating a 3D memory and a memory system. The 3D memory can include a stack including alternately stacked first dielectric layers and conductive layers, and a channel structure extending through the stack and including a second dielectric layer and a blocking layer disposed in this order from outside to inside. The second dielectric layer can have a dielectric constant greater than or equal to 3.9.

Abstract: Disclosed herein are memory device, method for program operations. In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Abstract: A three-dimensional memory device includes memory arrays stacking in a first direction. Each of the memory arrays includes a stack structure including interleaved conductive layers and first dielectric layers extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction. The conductive layers include word lines and a drain select gate line, and the drain select gate line is separated by a second dielectric layer in the second direction.

Abstract: The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.