Abstract: Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.

Abstract: Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.