Patents by Inventor Junbo PAN

Junbo PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991876
    Abstract: Provided are a semiconductor structure and a method for forming same. The method includes the following operations. Active areas and first isolation structures disposed at intervals are provided. Second isolation structures located between adjacent active areas are provided, and top surfaces of the second isolation structures are higher than or flush with top surfaces of the active areas. A mask layer are formed, pattern openings of which expose part of the top surfaces of the active areas, and the second isolation structures are located at two opposite sides of part of the active areas. The part of the active areas exposed by the pattern openings and part of the first isolation structures are etched to form intermediate grooves at least exposing part of surfaces of the active areas. Bit line structures are formed, which are electrically connected to top surfaces exposed by the intermediate grooves.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 21, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Junbo Pan, Jinghao Wang
  • Publication number: 20230079234
    Abstract: A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.
    Type: Application
    Filed: June 30, 2022
    Publication date: March 16, 2023
    Inventors: Jinghao WANG, Junbo PAN
  • Publication number: 20230055179
    Abstract: A preparation method of a metal connecting line includes: providing a base, where the base includes a metal conductive structure; patterned etching the base to expose a surface of the metal conductive structure; treating a surface of the base by oxygen-containing plasma to remove a charge on the surface of the metal conductive structure; and cleaning the surface of the metal conductive structure by hydrogen.
    Type: Application
    Filed: June 8, 2021
    Publication date: February 23, 2023
    Inventors: Ning XI, Junbo PAN
  • Publication number: 20230013786
    Abstract: The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.
    Type: Application
    Filed: September 27, 2021
    Publication date: January 19, 2023
    Inventor: Junbo PAN
  • Publication number: 20230008414
    Abstract: Provided are a semiconductor structure and a method for forming same. The method includes the following operations. Active areas and first isolation structures disposed at intervals are provided. Second isolation structures located between adjacent active areas are provided, and top surfaces of the second isolation structures are higher than or flush with top surfaces of the active areas. A mask layer are formed, pattern openings of which expose part of the top surfaces of the active areas, and the second isolation structures are located at two opposite sides of part of the active areas. The part of the active areas exposed by the pattern openings and part of the first isolation structures are etched to form intermediate grooves at least exposing part of surfaces of the active areas. Bit line structures are formed, which are electrically connected to top surfaces exposed by the intermediate grooves.
    Type: Application
    Filed: January 7, 2022
    Publication date: January 12, 2023
    Inventors: Junbo PAN, Jinghao WANG