Patents by Inventor Junchao DING

Junchao DING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTION
    Publication number: 20260212928
    Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 16, 2026
    Publication date: July 23, 2026
    Inventors: Liu LIU, Junchao DING, Yingming LIU, Jong Sun SEL, Yixin MA, Jinwoo LEE, Xi LIN
  • Additional silicide layer on top of staircase for 3D NAND WL contact connection
    Patent number: 12580018
    Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 17, 2026
    Assignee: INTEL NDTM US LLC
    Inventors: Liu Liu, Junchao Ding, Yingming Liu, Jong Sun Sel, Yixin Ma, Jinwoo Lee, Xi Lin
  • ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTION
    Publication number: 20230139346
    Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 13, 2021
    Publication date: May 4, 2023
    Applicant: Intel Corporation
    Inventors: Liu LIU, Junchao DING, Yingming LIU, Jong Sun SEL, Yixin MA, Jinwoo LEE, Xi LIN