Patents by Inventor Jun Cheng Huang
Jun Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141476Abstract: A method for manufacturing a target material is provided, including the steps of: disposing raw material powder on a substrate and melting the raw material powder by laser to form a target material layer; repeating the preceding process to allow a plurality of target material layers to form an integrated target material column; after cooling the target material column, removing the target material column from the substrate; and performing vacuum heat treatment on the target material column. Since the target material is additively manufactured and subjected to vacuum heat treatment, the target material has a finer and more uniform microstructure, thus improving the product quality.Type: ApplicationFiled: December 27, 2022Publication date: May 2, 2024Applicant: TAIWAN STEEL GROUP AEROSPACE ADDITIVE MANUFACTURING CORPORATIONInventors: William HSIEH, Bo-Chen Wu, Chii-Feng Huang, Jun-Cheng Wang
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Patent number: 9472612Abstract: A method includes forming first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: GrantFiled: March 15, 2016Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Wei Kuo, Cheng-Wei Luo, Hsiao-Tsung Yen, Jun-Cheng Huang, Min-Chie Jeng
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Publication number: 20160197137Abstract: A method includes forming first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Chin-Wei Kuo, Cheng-Wei Luo, Hsiao-Tsung Yen, Jun-Cheng Huang, Min-Chie Jeng
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Patent number: 9331013Abstract: A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: GrantFiled: May 24, 2013Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Jun-Cheng Huang, Chin-Wei Kuo, Min-Chie Jeng
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Publication number: 20140264742Abstract: A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: ApplicationFiled: May 24, 2013Publication date: September 18, 2014Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Jun-Cheng Huang, Chin-Wei Kuo, Min-Chie Jeng
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Patent number: 8686507Abstract: A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.Type: GrantFiled: September 6, 2006Date of Patent: April 1, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
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Patent number: 8319286Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.Type: GrantFiled: December 27, 2010Date of Patent: November 27, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
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Patent number: 8283726Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers.Type: GrantFiled: November 20, 2009Date of Patent: October 9, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
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Publication number: 20120001261Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.Type: ApplicationFiled: December 27, 2010Publication date: January 5, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
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Publication number: 20100059824Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions.Type: ApplicationFiled: November 20, 2009Publication date: March 11, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: TING CHIEH SU, MIN CHIE JENG, CHIN CHANG LIAO, JUN CHENG HUANG
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Patent number: 7642602Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.Type: GrantFiled: October 18, 2006Date of Patent: January 5, 2010Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
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Publication number: 20070284663Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.Type: ApplicationFiled: October 18, 2006Publication date: December 13, 2007Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang