Abstract: A display panel includes: a substrate including a first area, a second area, and a third area; a stacked structure corresponding to a plurality of display elements in the second area, the stacked structure including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a plurality of grooves in the third area, wherein the stacked structure includes at least one organic material layer that is disconnected by the plurality of grooves, at least one groove of the plurality of grooves is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

Abstract: A display device includes: a substrate having an opening; a plurality of display elements at a display area adjacent to the opening, the plurality of display elements each including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a metal stacked structure between the opening and the display area, and including: a first sub-metal layer having a first hole; and a second sub-metal layer under the first sub-metal layer and having a second hole, the second hole overlapping with the first hole and having a width greater than a width of the first hole.

Abstract: A display apparatus includes: a first pixel, a second pixel, and a third pixel respectively configured to emit different colors; a first quantum transformation layer arranged to correspond to an emission area of the first pixel, the first quantum transformation layer including first quantum dots and first metal nanoparticles; and a second quantum transformation layer arranged to correspond to an emission area of the second pixel, the second quantum transformation layer including second quantum dots and second metal nanoparticles, wherein an average size of the first quantum dots is different from an average size of the second quantum dots, and wherein an average size of the first metal nanoparticles is identical to an average size of the second metal nanoparticles.

Abstract: A display apparatus includes: a substrate including a component area, a display area, and a middle area provided between the component area and the display area; a thin-film transistor arranged in the display area; a display element including a pixel electrode, an intermediate layer, and an opposite electrode, wherein the pixel electrode is electrically connected to the thin-film transistor; a first organic insulating layer, a second organic insulating layer, and a passivation layer sequentially stacked on each other between the thin-film transistor and the pixel electrode; and a groove arranged in the middle area, wherein the groove divides an organic material layer included in the intermediate layer, wherein the groove is provided in multiple layers including an organic layer and an inorganic layer, wherein the organic layer is arranged on the substrate, and the inorganic layer is stacked on the organic layer.

Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.

Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.

Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.

Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.

Abstract: An organic light emitting display device includes a thin film transistor on a substrate including a display area having an inner light-emitting area and an outer light-emitting area and a peripheral area, a first conductive member connected to the thin film transistor, a first via insulation layer covering the first conductive member, a second conductive member on the first via insulation layer to overlap the outer light-emitting area and a part of the peripheral area, a second via insulation layer covering the second conductive member, a first electrode on the second via insulation layer to overlap the display area and a part of the peripheral area, an organic light emitting layer on the first electrode, and a second electrode on the organic light emitting layer. The second via insulation layer and the first electrode have a step structure between the inner and outer light-emitting areas.

Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.

Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.

Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.

Abstract: An organic light emitting display device includes a thin film transistor on a substrate including a display area having an inner light-emitting area and an outer light-emitting area and a peripheral area, a first conductive member connected to the thin film transistor, a first via insulation layer covering the first conductive member, a second conductive member on the first via insulation layer to overlap the outer light-emitting area and a part of the peripheral area, a second via insulation layer covering the second conductive member, a first electrode on the second via insulation layer to overlap the display area and a part of the peripheral area, an organic light emitting layer on the first electrode, and a second electrode on the organic light emitting layer. The second via insulation layer and the first electrode have a step structure between the inner and outer light-emitting areas.

Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.