Abstract: Disclosed is an electronic device including a power regulator; a processor; a connector comprising first power pins that electrically connect an external electronic device with the power regulator, and first data reception pins that are disposed adjacent to at least some of the first power pins and electrically connect second data transmission pins of a connector of the external electronic device with data reception terminals of the processor; and one or more first receiver capacitors that are electrically connected to the first data reception pins and to the processor in order to block power from leaking into the first data reception pins from the at least some of the first power pins.

Abstract: Disclosed is an electronic device including a power regulator; a processor; a connector comprising first power pins that electrically connect an external electronic device with the power regulator, and first data reception pins that are disposed adjacent to at least some of the first power pins and electrically connect second data transmission pins of a connector of the external electronic device with data reception terminals of the processor; and one or more first receiver capacitors that are electrically connected to the first data reception pins and to the processor in order to block power from leaking into the first data reception pins from the at least some of the first power pins.

Abstract: An electronic apparatus is provided with an arrangement of discrete circuit elements designed to reduce power consumption. Such an arrangement comprises a memory; a memory controller to generate a control signal which controls the memory according to a predetermined operating clock; and a transmission line disposed between the memory controller and the memory to allow the control signal to be transmitted to the memory, wherein the timing of the control signal is controlled by a change of the operating clock.

Abstract: An electronic apparatus is provided with an arrangement of discrete circuit elements designed to reduce power consumption. Such an arrangement comprises a memory; a memory controller to generate a control signal which controls the memory according to a predetermined operating clock; and a transmission line disposed between the memory controller and the memory to allow the control signal to be transmitted to the memory, wherein the timing of the control signal is controlled by a change of the operating clock.