Abstract: The present disclosure relates to an RNAi-inducing nucleic acid molecule and use thereof. An aspect of the disclosure relates to an RNAi-inducing nucleic acid molecule for inhibiting expression of myeloid differentiation primary response gene 88 (MyD88). Another aspect of the present disclosure relates to a pharmaceutical composition for treating or preventing age-related macular degeneration, compri the RNAi-inducing nucleic acid molecule.

Abstract: The present application relates to an asymmetric RNAi-inducing nucleic acid molecule which inhibits the expression of retinoid-related orphan nuclear receptor-beta (ROR-beta) and use thereof, and more particularly to an asymmetric RNAi-inducing nucleic acid molecule comprising an antisense strand comprising a sequence complementary to mRNA encoding ROR-beta, and a sense strand forming complementary bonds with the antisense strand, and a pharmaceutical composition for ameliorating or treating a retinal disease, comprising the asymmetric RNAi-inducing nucleic acid molecule.

Abstract: A memory device includes memory banks that each include a bank array having memory cells, a row decoder, and a column decoder. Each memory cell includes a capacitor and a transistor, a write circuit to store input data received at the memory device from a test device in the bank array, a read circuit to generate output data based on reading data stored in the bank array, a parity data management circuit to generate first parity data smaller than the input data using the input data, generate second parity data smaller than the output data using the output data, and generate third parity data using the first and second parity data, and an output circuit to output at least one of the first, second, and third parity data as verification data, in response to receipt of a request from the test device at the memory device.

Abstract: A memory device comprises a plurality of memory banks, each of the plurality of memory banks includes a bank array having a plurality of memory cells, a row decoder selecting at least one of word lines connecting to the plurality of memory cells, and a column decoder selecting at least one of bit lines connecting to the plurality of memory cells, and each of the plurality of memory cells includes a capacitor and a transistor, a write circuit configured to store input data received at the memory device from a test device in the bank array, a read circuit configured to generate output data based on reading data stored in the bank array, a parity data management circuit configured to generate first parity data having a size smaller than the input data using the input data, generate second parity data having a size smaller than the output data using the output data, and generate third parity data using the first parity data and the second parity data, and an output circuit configured to output at least one instan