Abstract: A method of forming a dielectric layer on a substrate. A first in situ steam generation (ISSG) procedure is performed to form a first oxide layer on the substrate. A silicon nitride layer is formed on the first oxide layer. A second ISSG procedure is performed to form a second oxide layer on the silicon nitride layer. Moreover, during the second ISSG procedure, the silicon nitride layer can be transformed into a nitrogen-containing second oxide layer.

Abstract: A method of fabricating a flash memory. A tunneling dielectric layer and a conductive layer are formed on a substrate. The conductive layer is patterned to form a floating gate. A source/drain region is formed in the substrate between the floating gates. A gate dielectric layer is formed. The gate dielectric layer includes an oxide layer formed on the floating gate by in-situ steam generation (ISSG). A control gate is formed on the gate dielectric layer.

Abstract: This invention relates to a method for making the gate dielectric layer, more particularly, to the method for making the interface between the gate dielectric layer and silicon substrate by using oxygen radicals and hydroxyl radicals. In the method, we send the wafers, which has passed through the cleaning process for the silicon substrate, to the chamber at first and then transmit the first reaction gas, which comprises the nitric monoxide and the oxygen or comprises the nitric monoxide and nitrogen, to the chamber to form a silicon nitride layer or a silicon oxynitride layer on the first surface of the silicon substrate to be a gate. Next, we transmit the second reaction gas, which comprises the oxygen and the hydrogen, to the chamber and make the second reaction gas to be dissociated into the oxygen radicals and the hydroxyl radicals.

Abstract: A re-oxidation process of a semiconductor device is described. A substrate having a stacked structure thereon is provided, wherein the stacked structure includes a polysilicon/tungsten silicide interface. A thin CVD oxide layer is formed on the substrate and the stacked structure with a chemical vapor deposition (CVD) process. Then, an oxidation process is performed to form a thermal oxide layer on the substrate and the stacked structure.

Abstract: A re-oxidation process of a semiconductor device is described. A substrate having a stacked structure thereon is provided, wherein the stacked structure includes a polysilicon/tungsten suicide interface. A thin CVD oxide layer is formed on the substrate and the stacked structure with a chemical vapor deposition (CVD) process. Then, an oxidation process is performed to form a thermal oxide layer on the substrate and the stacked structure.

Abstract: Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second region, with a mask layer formed on the surface of the sacrificial oxide layer. By defining and patterning the mask layer, a first opening and a second opening, having predetermined surface areas, are formed in portions of the first and second regions of the mask layer to expose portions of the. The sacrificial oxide layer has a surface area equal to the first predetermined surface area, and portions of the sacrificial oxide layer having a surface area equal to the second predetermined surface area. A linear nitrogen doping process is then performed to simultaneously implant nitrogen ions with a first and second predetermined concentration into the first and second region, through the first opening and the second opening, respectively.

Abstract: The present invention generally relates to provides a method for utilizing a re-oxidation step of a nitride layer to form a super thin nitride gate oxide layer. First, an oxide layer or a nitride oxide layer provided with a high nitrogen contain and a very thin thickness is growing on a semiconductor substrate, wherein the oxide layer can be provided with a large quantity nitrogen element by a nitrogen-penetrating treatment. Then, a second oxide layer is growing by a rapidly thermal step. Since in the second time to perform the oxidation of the substrate, the oxygen atom must penetrate the nitrogenized oxide layer to perform the oxidation with the substrate, so the present invention can decrease the oxidation rate and obtain a dense gate oxide layer with a good interface performance. The present invention can improve the disadvantage of too fast oxidation rate of the super thin gate oxide layer process and overcome the disadvantage of the difficult for obtaining a uniform and dense oxide layer.

Abstract: Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second region, with a mask layer formed on the surface of the sacrificial oxide layer. By defining and patterning the mask layer, a first opening and a second opening, having predetermined surface areas, are formed in portions of the first and second regions of the mask layer to expose portions of the. The sacrificial oxide layer has a surface area equal to the first predetermined surface area, and portions of the sacrificial oxide layer having a surface area equal to the second predetermined surface area. A linear nitrogen doping process is then performed to simultaneously implant nitrogen ions with a first and second predetermined concentration into the first and second region, through the first opening and the second opening, respectively.

Abstract: A method of improving quality of an interface between a gate and a gate oxide layer is disclosed. The method begins by providing a substrate with a gate oxide layer formed thereon. A nitrogen containing plasma treatment is then performed on the gate oxide layer, so that a top surface of the gate oxide layer is reacted to form a silicon oxy-nitride layer. A polysilicon layer is formed on the silicon oxy-nitride layer and subsequently patterned to form a polysilicon gate.

Abstract: A design for a trench DMOS transistor having improved current carrying capability is presented. The principal improvement lies in the periodic replacement of the individual cells in the array with a protection cell of a different size. When this is done it becomes possible to significantly increase the density of cells per unit area. This results in a corresponding improvement in the amount of channel area available to the device and hence an increase in its current carrying capability.