Abstract: A deep ultraviolet light-emitting diode is provided. A deep ultraviolet light-emitting diode according to one embodiment comprises: a substrate; an n-type semiconductor layer positioned on the substrate; a mesa which is disposed on the n-type semiconductor layer, comprises an active layer and a p-type semiconductor layer, and has a plurality of via-holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via-holes; a p-ohmic contact layer contacting the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer, wherein the p-pad metal layer is formed so as to surround the n-pad metal layer.

Abstract: A vertical gallium nitride transistor according to an exemplary embodiment of the present invention includes a semiconductor structure including a first semiconductor layer of a first conductivity-type having a first surface and sidewalls, a second semiconductor layer of the first conductivity-type surrounding the first surface and the sidewalls of the first semiconductor layer, and a third semiconductor layer of a second conductivity-type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other.

Abstract: Disclosed are a group III-V based transistor and a method for manufacturing same. The group III-V based transistor includes a laminated semiconductor structure having an upper surface and a lower surface and including a group III-V based semiconductor layer, and at least one 2DEG region extending from the upper surface of the laminated semiconductor structure to the lower surface thereof. A vertical-type GaN-based transistor using 2DEG can be provided by adopting the 2DEG region.

Abstract: Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain Schottky electrode disposed in the recess of the barrier layer, the recessed-drain Schottky electrode contacting the drain electrode.

Abstract: Exemplary embodiments of the present invention disclose a heterojunction transistor having a normally off characteristic using a gate recess structure and a method of fabricating the same. The heterojunction transistor may include a substrate, a channel layer disposed on the substrate and made of a first nitride-based semiconductor having a first energy bandgap, a first barrier layer disposed on the channel layer and made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, a gate electrode disposed in a gate control region of the first barrier layer, and a second barrier layer disposed in gate non-control regions of the first barrier layer and separated from the first barrier layer.

Abstract: Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain Schottky electrode disposed in the recess of the barrier layer, the recessed-drain Schottky electrode contacting the drain electrode.

Abstract: A vertical gallium nitride transistor according to an exemplary embodiment of the present invention includes a semiconductor structure including a first semiconductor layer of a first conductivity-type having a first surface and sidewalls, a second semiconductor layer of the first conductivity-type surrounding the first surface and the sidewalls of the first semiconductor layer, and a third semiconductor layer of a second conductivity-type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other.

Abstract: Disclosed are a ReRAM, which is a non-volatile memory device, and a production method therefor. A resistance-variable layer, which varies the resistance in accordance with an applied pulse, has a multilayered structure comprising 3 oxide films. Each oxide film consists of an oxide film of the same type as the neighbouring oxide film(s), but the oxygen ratios in the compositions of neighbouring oxide films differ from each other.

Abstract: Disclosed is a resistive memory simultaneously having rectifying characteristics and resistive characteristics according to a bias direction, wherein a resistive diode is interposed between electrodes at the top and bottom thereof. The resistive diode has a form in which a p-type resistive semiconductor layer is bonded to an n-type resistive semiconductor layer. When a high reverse bias is applied to the resistive diode, the resistive diode forms a conductive filament. When a forward bias is applied thereafter, a reset that destroys a portion of the formed conductive filament occurs, and as a result, a high resistance state is formed. Additionally, when a reverse bias is applied again, a set operation regenerating a conductive filament occurs. Thus, a low resistance state is achieved. Moreover, in order to achieve a resistive semiconductor layer and ohmic contact, and suppress the formation of a Schottky barrier, an ohmic contact layer is formed on the resistive diode.

Abstract: Disclosed are a ReRAM, which is a non-volatile memory device, and a production method therefor. A resistance-variable layer, which varies the resistance in accordance with an applied pulse, has a multilayered structure comprising 3 oxide films. Each oxide film consists of an oxide film of the same type as the neighbouring oxide film(s), but the oxygen ratios in the compositions of neighbouring oxide films differ from each other.

Abstract: A memory device includes a lower electrode layer formed over a substrate, a resistance layer including a metal nitride layer formed over the lower electrode layer, and an upper electrode layer formed over the resistance layer.