Patents by Inventor June Sugiura
June Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5580810Abstract: A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.Type: GrantFiled: April 4, 1995Date of Patent: December 3, 1996Assignee: Hitachi, Ltd.Inventors: Hisao Katto, June Sugiura, Nozomi Horino, Akira Endo, Yoshiharu Takeuchi, Yuji Arakawa
-
Patent number: 5416347Abstract: A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.Type: GrantFiled: October 13, 1992Date of Patent: May 16, 1995Assignee: Hitachi, Ltd.Inventors: Hisao Katto, June Sugiura, Nozomi Horino, Akira Endo, Yoshiharu Takeuchi, Yuji Arakawa
-
Patent number: 5352620Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: June 2, 1993Date of Patent: October 4, 1994Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
-
Patent number: 5194924Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: October 23, 1991Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
-
Patent number: 5136546Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converter parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.Type: GrantFiled: January 7, 1991Date of Patent: August 4, 1992Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
-
Patent number: 5098855Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of a LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: March 28, 1990Date of Patent: March 24, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
-
Patent number: 4984212Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.Type: GrantFiled: February 14, 1990Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
-
Patent number: 4918501Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: December 29, 1988Date of Patent: April 17, 1990Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
-
Patent number: 4905195Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of this parallel signal action.Type: GrantFiled: November 29, 1988Date of Patent: February 27, 1990Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
-
Patent number: 4872041Abstract: Disclosed is a semiconductor device, and method of manufacture thereof, the device having a conductive layer formed on a semiconductor substrate, with an insulating layer interposed between the substrate and conductive layer, and wherein a dense insulating layer is disposed at the sides of the conductive layer so as to cover the sides of the insulating layer on the substrate, the dense insulating layer acting to increase retention of charge in the conductive layer. The conductive layer can be the floating gate of a field effect transistor, with a control gate formed on the floating gate via another insulating layer whose sides can also be covered by the dense insulating layer. Such field effect transistor, having the floating gate, can be used as the memory cell of an EPROM, with the charge being the data stored in the cell. A field effect transistor of a peripheral circuit of the EPROM can also have the dense insulating layer applied so as to cover the sides of the gate oxide layer thereof.Type: GrantFiled: February 24, 1988Date of Patent: October 3, 1989Assignee: Hitachi, Ltd.Inventors: June Sugiura, Kazuhiro Komori
-
Patent number: 4830977Abstract: A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.Type: GrantFiled: January 27, 1988Date of Patent: May 16, 1989Assignee: Hitachi, Ltd.Inventors: Hisao Katto, June Sugiura, Nozomi Horino, Akira Endo, Yoshiharu Takeuchi, Yuji Arakawa
-
Patent number: 4788665Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.Type: GrantFiled: July 21, 1987Date of Patent: November 29, 1988Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
-
Patent number: 4731642Abstract: A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.Type: GrantFiled: February 22, 1985Date of Patent: March 15, 1988Assignees: Hitachi, Ltd., Hitachi Device Eng. Co.Inventors: Hisao Katto, June Sugiura, Nozomi Horino, Akira Endo, Yoshiharu Takeuchi, Yuji Arakawa
-
Patent number: 4691298Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.Type: GrantFiled: August 29, 1985Date of Patent: September 1, 1987Assignee: Hitachi, Ltd.Inventors: Minoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
-
Patent number: 4663645Abstract: A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.Type: GrantFiled: May 22, 1985Date of Patent: May 5, 1987Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
-
Patent number: 4651406Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.Type: GrantFiled: June 4, 1986Date of Patent: March 24, 1987Assignee: Hitachi, Ltd.Inventors: Shinji Shimizu, Kazuhiro Komori, Yasunobu Kosa, June Sugiura
-
Patent number: 4471373Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.Type: GrantFiled: January 7, 1981Date of Patent: September 11, 1984Assignee: Hitachi, Ltd.Inventors: Shinji Shimizu, Kazuhiro Komori, Yasunobu Kosa, June Sugiura
-
Patent number: 4451904Abstract: A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.Type: GrantFiled: January 26, 1981Date of Patent: May 29, 1984Assignee: Hitachi, Ltd.Inventors: June Sugiura, Yasunobu Kosa, Kazuhiro Komori, Ken Uchida, Shinji Shimizu