Abstract: A wide viewing angle holographic image display method and apparatus are disclosed. The wide viewing angle holographic image display apparatus includes a scan line unit and a control unit. The scan line unit includes a plurality of lateral scan lines that represent different angles, respectively. The control unit performs control so that different data are output at the respective different angles, represented by the lateral scan lines, using the plurality of lateral scan lines.

Abstract: A wide viewing angle holographic image display method and apparatus are disclosed. The wide viewing angle holographic image display apparatus includes a scan line unit and a control unit. The scan line unit includes a plurality of lateral scan lines that represent different angles, respectively. The control unit performs control so that different data are output at the respective different angles, represented by the lateral scan lines, using the plurality of lateral scan lines.

Abstract: A moving picture decoder further includes a plurality of switches in a mesh configuration, and at least one On-Chip Network (OCN) arranged in a star configuration and coupled to the plurality of switches. The On-Chip Network (OCN) includes a plurality of slave modules coupled to the On-Chip Network (OCN) and arranged in a star configuration.

Abstract: Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes recording the history of a sharer node in the sharer history table of the auxiliary memory, requesting share data with reference to the sharer history table of the auxiliary memory, and deleting share data stored in the distributed memory and updating the sharer history table of the auxiliary memory.

Abstract: There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Abstract: A memory mapping apparatus includes a core/memory selector adapted to select a core from among a plurality of cores, and select a memory from among a plurality of memories, a transfer path allocator adapted to allocate a data transfer path between the core and memory which are selected by the core/memory selector, and a DMA control signal setter adapted to set a signal to be controlled to a DMA Controller which controls a plurality of DMAs corresponding to data transfer paths between the cores and the memories.

Abstract: Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a node having a distributed memory and an auxiliary memory storing a sharer history table. The network load reducing method includes recording the history of a sharer node in the sharer history table of the auxiliary memory, requesting share data with reference to the sharer history table of the auxiliary memory, and deleting share data stored in the distributed memory and updating the sharer history table of the auxiliary memory.

Abstract: An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Abstract: Provided is an On-Chip network (OCN) based moving picture decoder. The moving picture decoder includes: a plurality of switches for providing a parallel data transmission path between a predetermined master module and the other master module, a parallel data transmission path between a predetermined master module and a predetermined slave module, and a parallel data transmission path between a predetermined slave module and the other slave module; and a plurality of On-Chip Networks (OCNs) for providing a local parallel data transmission path between predetermined slave modules and a parallel data transmission path between a slave module in a corresponding area and the switches, wherein a OCN structure of the moving picture decoder globally has a mesh structure with the switches as medium and locally has a star structure with each of the ONCs as medium.

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.