Abstract: A trace and debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core executes non-successive instruction in accordance with an address data of the program counter; (C) producing a trace break event in order to set the processor core to enter a debug mode if the processor core executes a non-successive instruction; (D) fetching a value of the program counter and a state of the processor core; and (E) sending the value and the state to a host to accordingly form a trace and debug message with respect to the processor core.

Abstract: A trace and debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core executes non-successive instruction in accordance with an address data of the program counter; (C) producing a trace break event in order to set the processor core to enter a debug mode if the processor core executes a non-successive instruction; (D) fetching a value of the program counter and a state of the processor core; and (E) sending the value and the state to a host to accordingly form a trace and debug message with respect to the processor core.

Abstract: A processor and method capable of automatically converting instruction mode to align a word boundary of a multi-mode instruction is disclosed, wherein the multi-mode instruction to be executed is from an L-bit instruction word. The L-bit instruction word contains an M-bit instruction or a plurality of N-bit instructions. When the L-bit word fetched is an M-bit instruction and its preceding L-bit word is an N-bit instruction, an N-bit instruction is converted into corresponding M-bit instruction when the N-bit instruction corresponds to an M-bit instruction, otherwise, at least one N-bit NOP instruction following the N-bit instruction is inserted.