Patents by Inventor Junedong Lee
Junedong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8963283Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: March 31, 2014Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8940617Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: November 21, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Publication number: 20140210039Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Patent number: 8716776Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: June 26, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8685806Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.Type: GrantFiled: June 3, 2013Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Junedong Lee, Dominic J. Schepis
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Publication number: 20140080281Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Patent number: 8652925Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: July 19, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8637958Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: GrantFiled: September 14, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi Todi, Geng Wang
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Publication number: 20130273715Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.Type: ApplicationFiled: June 3, 2013Publication date: October 17, 2013Inventors: Thomas W. Dyer, Junedong Lee, Dominic J. Schepis
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Patent number: 8536650Abstract: A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described.Type: GrantFiled: February 3, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Junedong Lee
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Patent number: 8482009Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.Type: GrantFiled: April 25, 2011Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Thomas Walter Dyer, Junedong Lee, Dominic J. Schepis
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Publication number: 20130043559Abstract: A method includes removing an exposed portion of a first portion of a substrate to define a first trench portion partially defined by the first portion of the substrate and expose a second portion of the substrate, the first portion of the substrate disposed on the second portion of the substrate, the second portion of the substrate including an N+ doped silicon material, and removing a portion the exposed second portion of the substrate with an isotropic etching process to define a second trench portion.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: International Business Machines CorporationInventors: JUNEDONG LEE, Xi Li, Paul C. Parries, Richard Wise, Hongwen Yan
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Patent number: 8354675Abstract: A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.Type: GrantFiled: May 7, 2010Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Oh-jung Kwon, Junedong Lee, Chengwen Pei, Geng Wang
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Publication number: 20130009277Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang
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Patent number: 8298908Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: GrantFiled: February 11, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang
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Publication number: 20120267754Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Patent number: 8128749Abstract: An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI substrate, or a seeded SOI substrate. The gettering layer may disposed under a buried oxide (BOX) layer. The gettering layer may be disposed on a backside of the substrate.Type: GrantFiled: October 4, 2007Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Junedong Lee, Devendra K. Sadana, Dominic J. Schepis
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Publication number: 20120012971Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: July 19, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Publication number: 20110272702Abstract: A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Oh-jung Kwon, Junedong Lee, Chengwen Pei, Geng Wang
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Publication number: 20110193193Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang