Abstract: The present disclosure discloses a flat-substrate heating apparatus including a module supporting plate having a plurality of unit module regions formed on an upper surface thereof; a plurality of VCSEL modules having a plurality of VCSEL devices and seated on the unit module regions of the module support plate, respectively; an electric power supplying board placed below the module support plate and configured to supply an electric power to the VCSEL module; and an electrode terminal electrically connecting the VCSEL module and the electric power supplying board while detachably securing them to upper and lower surfaces of the module support plate, wherein the module support plate has a coolant supplying unit formed therein and configured to supply coolant to the VCSEL module.

Abstract: A sealing device configured for use in a vacuum chamber between a reaction region of the vacuum chamber and an exhaust port includes a ring-shaped body with an upper surface and a lower surface. A distance between the upper surface and the lower surface of the sealing device is a thickness of the ring-shaped body. The thickness of the ring-shaped body differs along a circumference of the ring-shaped body such that the ring-shaped body has a wedge shape. The thickness of the ring-shaped body, around its circumference is dependent upon a structure of the exhaust port.

Abstract: Disclosed are a display device and a method for driving a pixel of the display device. The device and method is capable of securing a time to sense a threshold voltage of a driving transistor and of compensating for the threshold voltage during operation of the pixel. Each of a plurality of pixels has a 5T1C structure including first to fourth transistors and a driving transistor. The first to fourth transistors are configured to apply driving signals through first to fourth scan lines, respectively. Thus, even without increasing the number of driving signals applied to each pixel, a long time for sensing a threshold voltage of each pixel can be secured.

Abstract: A display device according to an exemplary embodiment of the present disclosure includes a light emitting diode and a pixel driving circuit which drives the light emitting diode, the pixel driving circuit includes a driving transistor which applies a driving current to the light emitting diode, a first transistor which applies a first reference voltage to a gate electrode of the driving transistor, a second transistor which applies a data voltage to the gate electrode of the driving transistor, a third transistor which applies a second reference voltage to a source electrode of the driving transistor, and a storage capacitor connected to the gate electrode and the source electrode of the driving transistor. According to the present disclosure, the threshold voltage Vth and the mobility of the driving transistors are internally compensated to improve an image quality.

Abstract: Disclosed are a display device and a method for driving a pixel of the display device. The device and method is capable of securing a time to sense a threshold voltage of a driving transistor and of compensating for the threshold voltage during operation of the pixel. Each of a plurality of pixels has a 5T1C structure including first to fourth transistors and a driving transistor. The first to fourth transistors are configured to apply driving signals through first to fourth scan lines, respectively. Thus, even without increasing the number of driving signals applied to each pixel, a long time for sensing a threshold voltage of each pixel can be secured.

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

Abstract: A sealing device configured for use in a vacuum chamber between a reaction region of the vacuum chamber and an exhaust port includes a ring-shaped body with an upper surface and a lower surface. A distance between the upper surface and the lower surface of the sealing device is a thickness of the ring-shaped body. The thickness of the ring-shaped body differs along a circumference of the ring-shaped body such that the ring-shaped body has a wedge shape. The thickness of the ring-shaped body, around its circumference is dependent upon a structure of the exhaust port.

Abstract: A sealing device configured for use in a vacuum chamber between a reaction region of the vacuum chamber and an exhaust port includes a ring-shaped body with an upper surface and a lower surface. A distance between the upper surface and the lower surface of the sealing device is a thickness of the ring-shaped body. The thickness of the ring-shaped body differs along a circumference of the ring-shaped body such that the ring-shaped body has a wedge shape. The thickness of the ring-shaped body, around its circumference is dependent upon a structure of the exhaust port.

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

Abstract: An electronic device includes a reception equalizer that performs, a first equalization on a first signal based on a first coefficient, and one or more second equalizations on one or more second signals based on the first coefficient, the one or more second signals being based on a second coefficient associated with one or more characteristics of a transmission equalizer of the external device, and circuitry that iteratively sends control information generated based on the first coefficient to the external device until a termination condition is satisfied with regard to the first coefficient, the control information causing the second coefficient to be increased or decreased, the iteratively sent control information causing a first absolute value of the first coefficient corresponding to a final equalization of the one or more second equalizations to become smaller than a second absolute value of the first coefficient corresponding to the first equalization.

Abstract: An orthogonal frequency division multiplexing (OFDM) transmission device transmits OFDM symbols to at least one reception device and includes an OFDM transmission processing unit which generates a plurality of OFDM symbols; a pilot insertion unit which inserts pilot tones into each of the plurality of OFDM symbols; and a control unit which controls the pilot insertion unit to insert the pilot tones according to a pilot insertion pattern which is selected to correspond to a communication environment from among a plurality of pilot insertion patterns.

Abstract: A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.

Abstract: An orthogonal frequency division multiplexing (OFDM) transmission system is provided which includes a data processing unit which generates a transmission signal using a plurality of tones including a reserved tone, a storage unit which stores Peak Reduction Kernel information according to the type of data symbol, and a compensation unit which retrieves the Peak Reduction Kernel information according to the type of data symbol from the storage unit and causes the retrieved information to be carried by the reserved tone included in the transmission signal. Therefore, a Peak-to-Average Power Ratio (PAPR) can be efficiently compensated.

Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.