Abstract: A substrate integrated coaxial line (SICL) array is proposed in this invention. The SICL array includes at least a single channel. The inner conductor is between the first outer conductor layer and the second outer conductor layer. The first dielectric layer is between the first outer conductor layer and the inner conductor layer. The second dielectric layer is between the inner conductor layer and the second outer conductor layer. The metal vias columns are across the structure in vertical direction. The first outer conductor layer, the second outer conductor layer and the metal vias columns form the outer conductor. Many single channels in horizontal and vertical directions form the array, and adjacent channels share outer conductors. Vertically adjacent channels share outer conductor layers, and horizontally adjacent channels share metal vias. The SICL array can be used as board level/package level/chip level interconnects.