Patents by Inventor Junfei Yu

Junfei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250380514
    Abstract: Disclosed is a clamping arrangement, comprising: a clamp circuit, arranged between an internal supply voltage supply rail (Vcc) and a second supply voltage supply rail (Vss) and configured to, on detection of a high-voltage ESD event at an external terminal, protect a protected circuit from the ESD high-voltage for a duration defined by an RC-timer; and an RC-interruption circuit configured to suspend the operation of the RC-timer and thereby extend the duration, wherein the RC-interruption circuit comprises; a detector configured to detect that a voltage at an input to the protected circuit is above a reference voltage, and a switch configured to provide a current path between a mid-node of the RC-timer and a one of the second voltage supply rail and the internal supply voltage supply rail, in response to the detector detecting that the voltage at the input to the protected circuit is above the reference voltage.
    Type: Application
    Filed: June 5, 2025
    Publication date: December 11, 2025
    Inventors: Gijs Jan de Raad, Mohan Yu, Shenglan Tang, Junfei Yu, Jiafei Yu, Houssam Arbess
  • Publication number: 20250315393
    Abstract: A hub device and method for transmitting signals between at least one controller and target devices on multiple bus segments through the hub device uses a plurality of drivers coupled a plurality of target ports that are configured to be operably coupled to the bus segments. An input/output driver controller is coupled to the plurality of drivers to disable the drivers during a time window to allow the target devices to drive the bus segments and to enable the drivers to drive a value on all the bus segments at an end of the time window. A frame decoder is coupled to the input/output driver controller and at least one controller port to transmit data between the at least one controller port and the target ports via input/output driver controller.
    Type: Application
    Filed: April 7, 2025
    Publication date: October 9, 2025
    Inventors: Vishal Suhas Choudhary, Vasanth Mundargi, Junfei Yu
  • Patent number: 11532936
    Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 20, 2022
    Assignee: NXP B.V.
    Inventors: Gijs Jan de Raad, Junfei Yu, Rongrong Tang, Haojing Wu
  • Publication number: 20220209527
    Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.
    Type: Application
    Filed: May 27, 2021
    Publication date: June 30, 2022
    Inventors: Gijs Jan de Raad, Junfei Yu, Rongrong Tang, Haojing Wu