Abstract: A display panel. The display panel includes an optical fingerprint region which is provided with a light-blocking layer and a protection layer, and the light-blocking layer is provided with a plurality of through holes; the protection layer includes a filling part; the filling part fills parts of regions in the through holes, the filling part is disposed surrounding and closely fitting side walls of the through holes, and the protection layer further includes a light-transmitting part, a height of the light-transmitting part is greater than or equal to depths of the through holes, and an included angle formed between a bottom wall of the filling part and a side wall of the light-transmitting part is an acute angle; or, the filling part fills a whole region in the through hole, and a material of the filling part is a light-transmitting material.

Abstract: A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.

Abstract: A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.

Abstract: A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

Abstract: The present application relates to a pixel arrangement structure, including first sub-pixels, second sub-pixels, third sub-pixels, and fourth sub-pixels. Centers of two of the first sub-pixels arranged opposite to each other and centers of two of the second sub-pixels arranged opposite to each other are taken as vertices and are connected to form a virtual quadrilateral. The virtual quadrilateral includes two equal sides arranged opposite to each other, a short side and a long side arranged opposite to each other and connected to vertices of the equal sides. The short side of the virtual quadrilateral is not parallel to the long side of the virtual quadrilateral. One of the third sub-pixels or one of the fourth sub-pixels is arranged in the virtual quadrilateral, and the third sub-pixel and the fourth sub-pixel emits light in a same color.

Abstract: A gate driving circuit and a driving method thereof, and a display device that belong to the field of display technology. The gate driving circuit includes an input module and a storage module. The input module is connected to each of a first node and a signal input terminal of the gate driving circuit and configured to control the potential of the first node according to the potential of the signal input terminal. An input terminal of the storage module is connected to the first node. The storage module is configured to store the potential of the first node and control the potential of an output terminal of the storage module according to the potential of the first node.

Abstract: The present application relates to a pixel arrangement structure, comprising a plurality of first pixel units and a plurality of second pixel units. The plurality of first pixel units and the plurality of second pixel units are alternately arranged in a first direction and a second direction. The first pixel units and the second pixel units respectively comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel is located at one side of an imaginary connecting line between a center of the third sub-pixel and a center of the fourth sub-pixel, and the second sub-pixel is located at another side of the imaginary connecting line between the center of the third sub-pixel and the center of the fourth sub-pixel. After the second pixel units are rotated by a predetermined angle, sub-pixel arrangement structures thereof are mirror-symmetrical to that of the first pixel units.

Abstract: A display panel includes two first sub-pixels and two second sub-pixels which are connected as a first virtual quadrilateral. Each of the two first sub-pixels includes a first subordinate sub-pixel and a second subordinate sub-pixel facing to each other and spaced apart from each other. One of two first vertices of the first virtual quadrilateral being located between the first subordinate sub-pixel and the second subordinate sub-pixel of one of the two first sub-pixels, the other one of the two first vertices being located between the first subordinate sub-pixel and the second subordinate sub-pixel of another one of the two first sub-pixels. Two second sub-pixels are respectively located at two second vertices of the first virtual quadrilateral. The two first vertices and the two second vertices are alternately arranged and spaced apart from each other. The display panel includes a third sub-pixel located within the first virtual quadrilateral.

Abstract: Disclosed are a pixel circuit and a driving method therefor. The pixel circuit includes: a driving module (110), a voltage writing module (120), a compensation module (130), a coupling module (140), and a first initialization module (150). The first initialization module (150) is connected to a second terminal N2 of the driving module (110). The first initialization module (150) is configured to control a magnitude of a current flowing through the driving module (110). The compensation module (130) is connected between a control terminal G and a first terminal N1 of the driving module (110). The compensation module (130) is configured to compensate for a threshold voltage of the driving module (110) in a compensation phase based on a voltage at the first terminal N1 of the driving module (110) obtained after the first terminal N1 is discharged via the driving module (110) and the first initialization module (150).

Abstract: A pixel circuit and a driving method therefor, and a display panel are provided. The pixel circuit includes a driver module, a signal supply terminal, a compensation module, and a coupling module. The compensation module is configured to compensate for a threshold voltage of the driver module in a compensation phase. The signal supply terminal supplies a fixed voltage to the coupling module in an initialization phase and supplies a data voltage to the coupling module in a data writing phase, the coupling module is configured to couple a voltage containing information about the data voltage to a control terminal of the driver module via the compensation module in the data writing phase, where the data writing phase is later than the compensation phase.

Abstract: Embodiments of the present application disclose a shift register, and a gate drive circuit and a driving method therefor. A first control module is configured to control, based on a signal of a first clock signal terminal, a signal of a second clock signal terminal, and a level of a second node, an initial signal and a first level signal to be transmitted to a first node. A second control module controls, based on the initial signal and a signal of a third clock signal terminal, a second level signal and the signal of the third clock signal terminal to be transmitted to the second node. An output module controls, based on a level of the first node, the signal of the second clock signal terminal to be transmitted to an output terminal of the shift register.

Abstract: A method and an apparatus for conformal boron doping of a three-dimensional structure. The method comprises: removing an oxide layer from a surface of a silicon-based three-dimensional (3D) substrate; forming, after removing the oxide layer, a first group of stacked films on a surface of the silicon-based three-dimensional substrate; forming a second group of stacked films on a surface of the first group of stacked films away from the silicon-based 3D substrate; depositing an aluminum oxide passivation layer on a surface of the second group of stacked films away from the first group of stacked films; and boron-doping the silicon-based 3D substrate through laser annealing or rapid thermal annealing, where the laser annealing or the rapid thermal annealing drives boron dopants, which comprises boron oxide, into the silicon-based 3D substrate via an auxiliary layer.

Abstract: A method for preparing a metallic cobalt thin film and a method for preparing a cobalt silicide thin film. A silicon-based three-dimensional substrate is preprocessed to obtain a preprocessed substrate. A cobalt buffer layer is forming in a first reaction chamber on the preprocessed substrate through first atom layer deposition (ALD), where a first gas serves as a carrier gas of the first ALD, and pulses of a first cobalt-based precursor gas and pulses of a first reaction gas are alternately introduced into the first reaction chamber. The metallic cobalt thin film is formed in a second reaction chamber on the cobalt buffer layer through second ALD, where a second gas serves as a carrier gas of the second ALD, and a second cobalt-based precursor gas and a second reaction gas are alternately introduced into the second reaction chamber in pulses.

Abstract: A pixel circuit and a driving method therefor, and a display panel. The pixel circuit includes a drive circuit, a first storage circuit, and a locking control circuit; where the drive circuit generates a drive current according to a potential difference between a control terminal and a first terminal of the drive circuit; the first storage circuit has a first terminal electrically connected to the control terminal of the drive circuit and a second terminal electrically connected to the first terminal of the drive circuit; a control terminal of the locking control circuit is configured to access a locking control signal, and a first terminal of the locking control circuit is electrically connected to the control terminal of the drive circuit; the second terminal of the first storage circuit or a second terminal of the locking control circuit is configured to access a data signal.

Abstract: Embodiments of the present application provide a display panel and a display device. The display panel includes: a substrate; an active layer disposed on the substrate; and a gate layer disposed on a side of the active layer facing away from the substrate, where the substrate includes an insulating dielectric film layer, a dielectric constant of the insulating dielectric film layer is less than a dielectric constant of the gate layer. The insulating dielectric film layer produces parasitic capacitance which affects a flow of carriers in the active layer. In the embodiments of the present application, a dielectric constant of the insulating dielectric film layer is less than a dielectric constant of the gate layer, so that the parasitic capacitance produced by the insulating dielectric film layer can be reduced, the influence of charges in the substrate on the carriers in the active layer can then be reduced.

Abstract: A method for manufacturing a MOS device, comprising: providing a substrate comprising a gate portion and a source-or-drain portion, where a through hole is formed in a dielectric layer disposed on the substrate and exposes a surface of the source-or-drain portion; doping the source-or-drain portion; amorphizing the doped source-or-drain portion to form an amorphous layer on a surface of the source-or-drain portion; oxidizing the source-or-drain portion to segregate dopants in adjacency of the amorphous layer; removing the oxidized amorphous layer; and forming a metal silicide on the surface of the source-or-drain portion. Contact resistance of a source and/or a drain is significantly reduced.

Abstract: The present disclosure provides a two-color LED light circuit and an LED light control circuit, including an LED light switch control module configured for connecting with a switch signal chip and an LED light assembly, an overcurrent protection module connected with the LED light switch control module and configured for detecting overcurrent of the LED light assembly and disconnecting current of the LED light switch control module, an overtemperature protection module connected with the LED light switch control module and configured for detecting overtemperature of the LED light control circuit and disconnecting current of the LED light switch control module, and an under-voltage protection module connected with an LED light assembly voltage input and the LED light switch control module, configured for detecting an input voltage of the LED light assembly and disconnecting the current of the LED light switch control module when the input voltage is too low.

Abstract: Disclosed are a gate drive circuit and a display panel. The gate drive circuit includes an output control module, a first transistor (T1), a second transistor (T2), and a voltage regulation module. The output control module is configured to control the first transistor (T1) and the second transistor (T2) to be alternately turned on, to alternately transmit a first output signal and a second output signal to an output terminal (O1) of the gate drive circuit. A first gate of the dual-gate transistor is connected to the output control module. The voltage regulation module is connected to a second gate of the dual-gate transistor, and is configured to regulate a voltage of the second gate of the dual-gate transistor, thereby regulating a threshold voltage of the dual-gate transistor and solving a problem of waveform distortion of a gate drive signal.

Abstract: A method for training a model in a virtual environment, a medium, an electronic device, and a computer program product. The method includes: an obtaining step, obtaining one or more initial parameters of each of one or more agents in the virtual environment, and causing each of one or more agents to generate one or more actions; an updating step, causing each agent to simultaneously perform the one or more actions in the virtual environment, so as to calculate, for each agent, one or more parameter variations that are respectively in one-to-one correspondence with the one or more initial parameters, and updating, based on the one or more initial parameters and the one or more parameter variations, to obtain one or more subsequent parameters of each agent in the virtual environment. It enhances scalability and reusability of simulating a game environment, increases the speed of simulating the game environment, and overall reduces the simulation time.