Patents by Inventor Junfeng Zhao

Junfeng Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170300419
    Abstract: A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Applicants: HUAWEI TECHNOLOGIES CO.,LTD., Fudan University
    Inventors: RenHua Yang, Junfeng Zhao, Wei Yang, Yuangang Wang, Yinyin Lin
  • Patent number: 9778688
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jiamiao Tang, Junfeng Zhao, Michael P. Skinner, Yong She, Jiun Hann Sir, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
  • Publication number: 20170278821
    Abstract: Some forms relate to an electronic assembly (10) that includes a die (11) that includes an upper surface (12) and a conductive column (13) extending from the upper surface (12) such that the conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11). Other forms relate to an electronic package (19) that includes a stack (20) of electronic assemblies (10) where each electronic assembly (10) includes a die (11) that having an upper surface (12) and a plurality of conductive columns (13) extending from the upper surface (12) such that each conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11), and wherein the stack (20) of electronic assemblies (10) is arranged in an overlapping configuration such the plurality of conductive columns (13) on each electronic assembly (10) are not covered by another electronic assembly (10).
    Type: Application
    Filed: October 3, 2014
    Publication date: September 28, 2017
    Inventors: Junfeng ZHAO, Cheng YANG
  • Patent number: 9767900
    Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 19, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiangshui Miao, Yi Li, Yaxiong Zhou, Ronggang Xu, Junfeng Zhao, Zhulin Wei
  • Publication number: 20170263295
    Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Shihai Xiao, Wei Yang, Junfeng Zhao
  • Patent number: 9740418
    Abstract: A storage unit includes a U-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port. The U-shaped magnetic track includes a first port, a second port, a first storage area, and a second storage area. By controlling input voltages of the first port, the second port, the first drive port, and the second drive port and driving the first drive circuit, a current pulse is generated in the first storage area, and a magnetic domain wall in the first storage area is driven to move. By controlling the input voltages of the first port, the second port, the first drive port, and the second drive port and driving the second drive circuit, a current pulse is generated in the second storage area, and a magnetic domain in the second storage area is driven to move.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: August 22, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yinyin Lin, Zhulin Wei, Junfeng Zhao, Wei Yang, Yarong Fu, Kai Yang
  • Patent number: 9741418
    Abstract: A write apparatus and a magnetic memory, where the write apparatus includes a first drive port, a second drive port, a first information storage area, a second information storage area, and an information buffer. A first area locates between the first information storage area and the information buffer. A second area locates between the second information storage area and the information buffer. The first information storage area, the second information storage area, and the information buffer are made of a first magnetic material. The first area and the second area are made of a second magnetic material. Magnetic energy of the first magnetic material is higher than magnetic energy of the second magnetic material. The write apparatus can ensure write stability of the magnetic memory.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 22, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yarong Fu, Junfeng Zhao, Yuangang Wang, Wei Yang, Yinyin Lin, Kai Yang
  • Publication number: 20170206958
    Abstract: A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 20, 2017
    Inventors: Rui He, Ronggang Xu, Junfeng Zhao
  • Publication number: 20170179082
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Application
    Filed: January 9, 2017
    Publication date: June 22, 2017
    Inventor: Junfeng Zhao
  • Publication number: 20170153822
    Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.
    Type: Application
    Filed: February 9, 2017
    Publication date: June 1, 2017
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun XU, Junfeng ZHAO, Yuangang WANG
  • Patent number: 9653099
    Abstract: An information storage apparatus includes a magnetic track, a writer, and a reader, where the magnetic track includes a number of magnetic domains. Each magnetic domain is divided into at least two magnetic regions, and the writer is disposed on the magnetic track, and configured to write information to the at least two magnetic regions of each magnetic domain. The reader, disposed on the magnetic track, is configured to read the written information from the at least two magnetic regions. Therefore, multiple pieces of valid information are written to one magnetic domain of the magnetic track, thereby increasing storage density of the magnetic track, and expanding a storage capacity of the storage apparatus.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 16, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yinyin Lin, Yarong Fu, Kai Yang, Wei Yang, Yuangang Wang, Junfeng Zhao
  • Patent number: 9653178
    Abstract: A storage device, a memory, and a method for controlling a storage device, where the storage device includes a comb-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port, where the comb-shaped magnetic track includes a first storage area, a second storage area, and a comb handle, and the first storage area and the second storage area include more than two memory bars.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 16, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yinyin Lin, Zhulin Wei, Junfeng Zhao, Wei Yang, Yarong Fu, Kai Yang
  • Publication number: 20170133089
    Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Zhen Li, Qiang He, Xiangshui Miao, Ronggang Xu, Junfeng Zhao, Shujie Zhang
  • Publication number: 20170133090
    Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Zhen Li, Qiang He, Xiangshui Miao, Ronggang Xu, Junfeng Zhao, Zhulin Wei
  • Publication number: 20170133074
    Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Inventors: Kai Yang, Junfeng Zhao, Yuangang Wang, Wei Yang, Yinyin Lin, Yarong Fu
  • Publication number: 20170133072
    Abstract: A magnetic storage track and a magnetic memory are provided. The magnetic storage track includes multiple stacked storage track units. A transition layer is disposed between two neighboring storage track units. The transition layer is constituted by a semiconductor material deposited on an insulating material, and includes a gating circuit and a read/write apparatus. Because the magnetic storage track includes multiple stacked storage track units, a track length of the magnetic storage track is constituted by track lengths of the multiple storage track units. Therefore, when a storage capability of the magnetic storage track needs to be improved, the track length of the magnetic storage track may be increased by adding the storage track unit.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 11, 2017
    Inventors: Yinyin Lin, Kai Yang, Shujie Zhang, Junfeng Zhao, Wei Yang, Yarong Fu
  • Patent number: 9627358
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 9589934
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Publication number: 20170047119
    Abstract: A data storage method, a storage apparatus and a computing device are disclosed. The method includes receiving a presetting command sent by a CPU, where the presetting command instructs to write 1 to a location, which corresponds to a cache line, in memory; writing, according to the presetting command, 1 to the location, which corresponds to the cache line, in the memory; receiving a write command sent by the CPU of writing data in the cache line to the memory; and writing, according to the write command, data 0 in the cache line to a location, which corresponds to the data 0, in the memory.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Jun Xu, Junfeng Zhao
  • Publication number: 20170040982
    Abstract: A latch and a D flip-flop, where the latch includes a switch, a resistive random-access memory, a bleeder circuit, and a voltage converter. The voltage converter is configured to output an output signal of the latch according to an input signal of the latch when the switch is in an on state, where the output signal remains consistent with the input signal. When the switch changes from the on state to an off state, the resistive random-access memory is configured to work together with the bleeder circuit to enable an output signal of the latch when the switch is in the off state to remain consistent with an output signal of the latch when the switch is in the on state, thereby implementing a nonvolatile latching function. A circuit structure of the latch is simple and integrity of an existing logic circuit can be improved.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Xiangshui Miao, Yi Li, Yaxiong Zhou, Ronggang Xu, Junfeng Zhao, Shujie Zhang