Patents by Inventor Jung Ahn
Jung Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070285519Abstract: The present invention relates to an image signal transmission method in a network camera system, and more particularly, to a network camera system and an image signal transmission method in which a low resolution image formed by down-scaling a high resolution image photographed by a high resolution camera is displayed via a display means of a DVR system, and the high resolution image is compressed to be stored in a memory means of the DVR system, thereby preventing overload on the system that may occur due to compressing, transmitting, or decompressing a plurality of high resolution image signals.Type: ApplicationFiled: September 15, 2005Publication date: December 13, 2007Applicant: UDP CO., LTD.Inventors: Jung Ahn, Sung Kang
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Publication number: 20070178237Abstract: The invention provides a method for patterning coatings which includes the steps of: a) applying coatings onto a flat plate; b) allowing the coatings applied to the flat plate to contact with protrusions of a substrate so as to transfer portions of the coatings on the flat plate which contact with the protrusions of the substrate to the protrusions of the substrate from the flat plate, the substrate having unevenness formed with the protrusions and grooves; and c) allowing the coatings remaining on the flat plate or on the protrusions of the substrate to contact with a print surface of a print object so as to transfer the coatings to the print object. The method has simple processes, and ensures high precision and high speed in patterning functional materials, preferalby, electronic materials.Type: ApplicationFiled: July 31, 2006Publication date: August 2, 2007Inventors: Dong Shin, Ji Kim, Dae Kim, Sung Kim, Kyung Choi, Hee Park, Jung Ahn, Jae Choi, Sang Yoo, Yoon Heo, Han Kim, Jeong Yoon
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Publication number: 20070166918Abstract: A non-volatile memory device includes a plurality of select lines and a plurality of word lines formed over a semiconductor substrate, a contact plug formed between the select lines, and a conductive interference shielding line formed between the select line and a word line adjacent to the select line and isolated from the semiconductor substrate.Type: ApplicationFiled: December 29, 2006Publication date: July 19, 2007Applicant: Hynix Semiconductor Inc.Inventors: Sang Hyun Oh, Jung Ahn, II Young Kwon
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Publication number: 20070087538Abstract: A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.Type: ApplicationFiled: June 2, 2006Publication date: April 19, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jum Kim, Jung Ahn
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Publication number: 20070010089Abstract: A method of forming a semiconductor device includes forming a contact hole in a first interlayer insulating layer that is provided on a semiconductor substrate. The contact hole has a sidewall defined by the first interlayer insulating layer. A first conductive layer is provided within the contact hole. The first conductive layer directly contacts the first interlayer insulating layer that defines the sidewall of the contact hole. The first conductive layer is etched to define a recess within the contact hole, the recess being provided directly above the first conductive layer. An interface metal layer is provided within the recess. A second interlayer insulating layer is formed on the interface metal layer. The second interlayer insulating layer is etched to expose the interface metal layer. A second conductive layer is deposited on the exposed interface metal layer to form a bit line.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Applicant: Hynix Semiconductor Inc.Inventors: Jung Ahn, Seok Lee
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Publication number: 20060252257Abstract: A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.Type: ApplicationFiled: May 2, 2006Publication date: November 9, 2006Applicant: Hynix Semiconductor, Inc.Inventors: Jung Ahn, Byung Park
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Publication number: 20060076886Abstract: The present invention discloses an encapsulation cap which not only seals simultaneously structural elements formed on two substrates but also has sufficient moisture-absorbing function by using only one getter (moisture absorbent) attached thereto, and a display device using the same. For separating structural elements formed on the glass substrate from the exterior, an encapsulation cap according to the present invention comprises a first surface on which a first recess is formed; and a second surface which is opposite to the first surface and has a second recess formed thereon, wherein the first surface is attached to a first substrate on which structural elements are formed, the second surface is attached to a second substrate on which structural elements are formed, and the structural elements formed on the first and second substrates are received in the first and second recess, respectively.Type: ApplicationFiled: October 7, 2005Publication date: April 13, 2006Inventor: Jung Ahn
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Publication number: 20060076884Abstract: The present invention relates to an organic electroluminescent device for preventing overflow of a sealant. The organic electroluminescent device including a cell section which has a plurality of pixels formed on a substrate has at least one sealant overflow preventing section and a cell cap. The sealant overflow preventing section is formed on the substrate around the cell section. The cell cap has a shape corresponding to the sealant overflow preventing section, and is adhered to the substrate through a sealant. In the organic electroluminescent device of the present invention, a cell cap inserting section is inserted between sealant overflow preventing sections so that the length of a pathway through which a sealant moves is augmented. Hence, the sealant may not be overflowed into the internal space of the cell cap.Type: ApplicationFiled: October 7, 2005Publication date: April 13, 2006Inventor: Jung Ahn
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Publication number: 20060045130Abstract: An electronic device employing an efficient network protocol stack. The protocol stack comprises a network-level protocol layer configured to provide a transmission service for transferring data to and from a computer network, and a device-level protocol layer configured to send and receive information specific to an interface of the electronic device over the network via the transmission service of the network-level protocol layer. Alternately, each of the network-level protocol layer and the device-level protocol layer may be employed individually with other network protocol layers to construct a functioning network protocol stack.Type: ApplicationFiled: July 22, 2005Publication date: March 2, 2006Inventors: Han-gyoo Kim, Kyung Kim, Il-gu Hong, Jung Ahn, Jun Park, Han Lim
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Publication number: 20060011813Abstract: A CMOS image sensor with improved sensitivity includes a main pixel array region of an active pixel array region formed on a semiconductor substrate. A passivation layer is formed over the sensor, and it is at least partially removed from the main pixel array region, such that incident light being detected by the main pixel array does not pass through the passivation layer. Optical absorption and refraction caused by the material of the passivation layer are eliminated, resulting in an image sensor with improved optical sensitivity.Type: ApplicationFiled: January 27, 2005Publication date: January 19, 2006Inventors: Young Park, Ki Kim, Bum Kim, Jeong Bae, Yu Ahn, Jung Ahn, Soo Lee, Yong Lee, Sung Hwang
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Publication number: 20050147785Abstract: The present invention provides nonwoven fiber materials, and methods for making the same, useful for loop materials in hook and loop mechanical attachment systems, the nonwoven materials having crimped monocomponent fibers having substantially circular cross sections, and the webs may further contain uncrimped fibers. The invention also provides disposable articles comprising nonwoven loop materials including disposable personal care absorbent articles such as diapers, feminine care sanitary napkins, and adult incontinence articles, and disposable protective articles such as surgical drapes and gowns and other protective apparel.Type: ApplicationFiled: March 2, 2005Publication date: July 7, 2005Inventors: Jung Ahn, Charles Bolian, JeaSeung Chin, Brian Forbes, SooGyung Jung, ByungSoo Kim, Jin Lee, Xin Ning, KueYoung You
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Publication number: 20050101089Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.Type: ApplicationFiled: December 3, 2004Publication date: May 12, 2005Inventors: Jum Kim, Sung Jung, Jung Ahn, Young Shin, Young Lee
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Publication number: 20050048723Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and tType: ApplicationFiled: June 30, 2004Publication date: March 3, 2005Inventors: Min Lee, Hee Chang, Jum Kim, Jung Ahn
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Publication number: 20050048718Abstract: Disclosed is a method for manufacturing a flash memory device. In a process of forming a flash memory cell and a select transistor through a process of forming a polysilicon layer for a floating gate, a process of forming a dielectric layer and a process of forming a polysilicon layer for a control gate, the dielectric layer is formed and the dielectric layer in a region where a select transistor will be formed is then removed, thereby forming a select gate line in which the polysilicon layer for the floating gate and the polysilicon layer for the control gate are electrically connected.Type: ApplicationFiled: June 30, 2004Publication date: March 3, 2005Inventors: Jung Ahn, Jum Kim