Patents by Inventor Jung-An Wang

Jung-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990383
    Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240163407
    Abstract: A projection system and a control method thereof are provided. The projection system includes a projector. The projector comprises a projection module and a processor. The processor is electrically coupled to the projection module. The projector confirms whether a first triggering event is detected and turns on a sleep aid mode in response to the first triggering event. The sleep aid mode corresponds to at least one control parameter. In the sleep aid mode, the projection module plays at least one multimedia file according to the at least one control parameter. The processor adjusts at least one parameter value of the at least one control parameter to adjust the at least one multimedia file correspondingly. The projector confirms whether a second triggering event is detected and the projection module stops playing the at least one multimedia file and turns off the sleep aid mode in response to the second triggering event.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 16, 2024
    Applicant: Optoma Corporation
    Inventors: Yuan-Mao Tsui, Hsien-Cheng Yuan, Chia-Chien Wu, Wei-Jung Wang
  • Patent number: 11985514
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive information identifying a sidelink discontinuous reception (DRX) configuration, that is different from an access link DRX configuration, associated with operation in a sidelink communication deployment. The UE may monitor a physical downlink control channel (PDCCH) discontinuously using the sidelink DRX configuration. Numerous other aspects are described.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: May 14, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Ho Ryu, Sony Akkarakaran, Junyi Li, Tao Luo, Juan Montojo, Jelena Damnjanovic, Hua Wang
  • Patent number: 11985637
    Abstract: There is disclosed a User Equipment for a MulteFire wireless communication network. The User Equipment comprises processing circuitry and a transmitter, the User Equipment being adapted for utilizing the processing circuitry and the transmitter for performing a Listen-Before-Talk (LBT) procedure for one or more transmission bandwidths; transmitting Physical Uplink Shared CHannel (PUSCH) signaling in a PUSCH subframe on one or more interlaces within the one or more transmission bandwidths; and transmitting Sounding Reference Signaling on the one or more interlaces in the PUSCH subframe.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: May 14, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Meng Wang, Jung-Fu Cheng, Fredrik Lindqvist, Amitav Mukherjee, Henrik Sahlin
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240153949
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Publication number: 20240148933
    Abstract: The present invention is directed to compressed hemostatic tablets or forms comprising a fibrous non-woven oxidized cellulose (OC or ORC) multilayer material compressed into a form stable tablet, further comprising calcium salt, with the tablets rapidly expandable on contact with blood or blood plasma. The compressed forms may further comprise a multi-arm PEG-SG and are dimensionally, preferably with regard to length and width, stable for at least 48 hours after compression. In some embodiments, the compressed forms will expand upon contact with blood from 1.5 to 5 times of tablet length in 5 seconds; from 2 to 6 times of tablet length in 20 seconds; and from 3 to 6 times of tablet length in 5 minutes. The compressed forms are effective in hemostasis in heparinized blood.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Applicant: Ethicon, Inc.
    Inventors: Yi-Lan Wang, Tien-Jung Lee
  • Publication number: 20240154520
    Abstract: A power factor correction (PFC) converter comprises an inductor, a main switch, a voltage divider, a diode, and a controller. The main switch controls the inductor performing magnetization and demagnetization, wherein a voltage difference between two ends of the main switch is a switch voltage. The voltage divider divides the switch voltage and generates a division voltage. The controller performs the following operations periodically in general mode: turning on the main switch; turning off the main switch after the main switch is turned on for a period of time; obtaining the switch voltage according to the division voltage, and determining the period of time for which the main switch is turned on next time according to the switch voltage and a predetermined output voltage of the PFC converter; and obtaining an output voltage according to the switch voltage during a period of time after the main switch is turned off.
    Type: Application
    Filed: March 30, 2023
    Publication date: May 9, 2024
    Applicant: Diodes Incorporated
    Inventors: Haoming Chen, Yi-Chun Wang, Koyen Lee, Feng-Jung Huang
  • Publication number: 20240154722
    Abstract: A method and a system are provided in which a message is encoded, by a neural encoder, to generate a codeword having a first length corresponding to a first code rate of the neural encoder. A number of components of the codeword corresponds to the first code rate. At least one of repeating the components or puncturing at least one of the components is performed to generate a rate-matched codeword having a second length corresponding to a second code rate. The rate-matched codeword is estimated and modified to generate an estimated codeword having the first length corresponding to the first code rate of a neural decoder. The estimated codeword is decoded, by the neural decoder, to generate an estimated message.
    Type: Application
    Filed: September 20, 2023
    Publication date: May 9, 2024
    Inventors: Linfang WANG, Hamid SABER, Homayoon HATAMI, Mohammad Vahid JAMALI, Jung Hyun BAE
  • Patent number: 11980016
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Patent number: 11979903
    Abstract: A base station may instruct a UE to use at least one weighting factor associated with a CR for the UE, and the UE may apply the at least one weighting factor to the one or more resources scheduled for the PSSCH transmission to determine the CR. The UE may transmit the PSSCH in the one or more resources of the at least one slot based on the determined CR being less than or equal to a CR threshold value. The at least one weighting factor may be applied to the one or more resources in each of multiple slots scheduled for transmission of a PSSCH.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 7, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Hua Wang, Sony Akkarakaran, Jung Ho Ryu, Tao Luo, Junyi Li
  • Publication number: 20240144966
    Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a first lower shield, a first sensor disposed over the first lower shield, a first upper shield disposed over the first sensor, a read separation gap (RSG) disposed on the first upper shield, a second lower shield disposed over the RSG, a second sensor disposed over the second lower shield, and a second upper shield disposed over the second sensor. In some embodiments, the second lower shield comprises a CoFeHf layer. In another embodiment, the second lower shield is a synthetic antiferromagnetic multilayer comprising a first shield layer, a second shield layer, and a CoFe/Ru/CoFe anti-ferromagnetic coupling layer or a Ru layer disposed therebetween, the first and second shield layers comprising NiFe and CoFe. In yet another embodiment, the second lower shield comprises layers of Ru, IrMn, and NiFe.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Chen-Jung CHIEN, Goncalo Marcos BAIÃO DE ALBUQUERQUE, Chih-Ching HU, Yung-Hung WANG, Ming JIANG
  • Publication number: 20240145461
    Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 2, 2024
    Applicant: Innolux Corporation
    Inventors: Ker-Yih Kao, Tong-Jung Wang, Wen-Chieh Lin, Ming-Chun Tseng, Yi-Hung Lin
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240136251
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20240130182
    Abstract: A display is provided. The display device includes a display area and a non-display area located around the display area; a base layer; an organic light-emitting diode (OLED) that is located on the base layer in the display area; and a first crack detection line that is located on the base layer in the non-display area; wherein the first crack detection line comprises a first line that extends substantially in a first direction along a first edge of the display area, a second line that is separated from the first line and extends substantially in the first direction, and a third line that is connected to an end of the first line and an end of the second line, wherein a cross-sectional shape of the first line in a second direction crossing the first direction is inversely tapered.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: Hun KIM, Yong Jin KIM, Soon Jung WANG, Keun Soo LEE, Jae Ho LEE, Kyung Chan CHAE
  • Publication number: 20240128868
    Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Jung Chang, Shao-Ming Chang, Tsan-He Wang, Jiing-Horng Wang, Yu-Pin Tseng
  • Publication number: 20240123311
    Abstract: An artificial shuttlecock includes a ball head, a plurality of feathers, and a plurality of stems. Each of the feathers includes a notch. The notch is disposed on an outer edge of the feather. A ball head end of the stem is connected to the ball head, and a feather end is connected to the feather. The stem includes a body, which tapers from the end close to the ball end to the feather end. The end of the body close to the ball end has a first width, and the body has a second width at the feather. The first width is between 2.1 mm and 2.4 mm, and the second width is between 0.4 mm and 0.6 mm.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 18, 2024
    Inventors: SHU-JUNG CHEN, TZU-WEI WANG, HSIN-CHEN WANG
  • Patent number: 11963172
    Abstract: This disclosure provides systems, methods, and apparatuses, including computer programs encoded on computer storage media, for wireless communication, including techniques for sidelink resource allocation and communication. In some aspects, a user equipment (UE) may receive from a base station a single message that indicates a first transmission opportunity for transmission of information from the UE to a second UE and that indicates one or more additional transmission opportunities for at least one subsequent transmission of information from the UE to the second UE. The UE may transmit the information to the second UE in the first transmission opportunity. The UE may also retransmit the information to the second UE in at least one of the one or more additional transmission opportunities responsive to the transmission of the information in the first transmission opportunity being unsuccessful. Other aspects and features are also claimed and described.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 16, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Ho Ryu, Sony Akkarakaran, Tao Luo, Junyi Li, Hua Wang, Jelena Damnjanovic, Juan Montojo