Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: An operating method of a memory controller configured to control a nonvolatile memory device including a plurality of memory cells is provided. The operating method includes: programming evaluation data into desired memory cells among the plurality of memory cells; performing initial verify shift (IVS) charge loss evaluation on the desired memory cells after a time elapses from a time point when the evaluation data is programmed, the IVScharge loss evaluation including an operation of detecting threshold voltage variation of the desired memory cells over a period based on the time elapsed from the time point when the evaluation data is programmed; and storing a result of the IVScharge loss evaluation; and adjusting levels of a plurality of read voltages used in the nonvolatile memory device based on the stored result of the charge loss evaluation.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: An operating method of a memory controller configured to control a nonvolatile memory device including a plurality of memory cells is provided. The operating method includes: programming evaluation data into desired memory cells among the plurality of memory cells; performing initial verify shift (IVS) charge loss evaluation on the desired memory cells after a time elapses from a time point when the evaluation data is programmed, the IVScharge loss evaluation including an operation of detecting threshold voltage variation of the desired memory cells over a period based on the time elapsed from the time point when the evaluation data is programmed; and storing a result of the IVScharge loss evaluation; and adjusting levels of a plurality of read voltages used in the nonvolatile memory device based on the stored result of the charge loss evaluation.

Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.

Abstract: Storage devices herein include a non-volatile memory and a controller configured to perform a read operation on a physical page of the non-volatile memory in response to a read request on a logical page of the non-volatile memory from a host. The controller may include a mapping manager configured to manage a plurality of logical blocks by a logical unit. The mapping manager may include a unit map table including a correlation between the logical unit and a physical unit corresponding to the logical unit. Additionally, the mapping manager may be configured to change a mapping method according to whether the unit map table includes a physical unit corresponding to a logical unit including a logical page requested by the host. Related user devices and electronic devices are also provided.

Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.

Abstract: A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A method of managing a page buffer of a non-volatile memory device comprises programming least significant bit (LSB) page data from an LSB page buffer into a page of memory cells, and retaining the LSB page data in the LSB page buffer until most significant bit (MSB) page data corresponding to the LSB page data is programmed in the page.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.

Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.

Abstract: A semiconductor storage device having an improved write performance is disclosed. The semiconductor storage device includes a plurality of memory devices, with each memory device associated with a logical address space comprising contiguous logical addresses. A controller of the semiconductor storage device is configured to allocate a plurality of meta data groups for each memory device, with each meta data group assigned a set of logical addresses of the logical address space. The controller may also configured to assign a first logical address of a logical address space to a first meta data group and a second logical address of the logical address space, contiguous to the first logical address, to a second meta data group, where the second meta data group is different than the first meta data group.

Abstract: A method of writing meta data in a semiconductor storage device in relation to a maximum number of written meta data pages N. The method stores write data in a buffer and loads meta data in a meta memory, writes the write data to the storage medium and updates the meta data. The updated meta data is stored upon determining a number of written meta data pages in an updated meta data region, and only exceeding the maximum number of written meta data pages N, a meta data write operation is performed.

Abstract: A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A semiconductor device with flash memory includes; a log type determining unit configured to select log type from among a plurality of log types with respect to a log block storing program data requested to be programmed in the flash memory and generate a control signal indicating information indicating the selected log type, and a plurality of log units configured to store program data in the log block having a corresponding log type in response to the control signal, wherein the log type determining unit converts a first type log block formed by a first log type and included in a first type log unit from among the plurality of log units into second type log block formed by a second log type and converts the log block included in a second type log unit from among the plurality of log units into the first type log blocks, the first log type being different from the second log type.