Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.

Abstract: A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Abstract: An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.

Abstract: Systems and methods for an integrated circuit layout is disclosed. The integrated circuit layout includes a first block including multiple first cells, each of which has a first cell height, and a second block including multiple second cells, each of which has a second cell height. The first block is disposed next to the second block with a spacing that is either equal to zero or less than any of the first or second cell heights.

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

Abstract: A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first pin and the second pin in the first group of pins together thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit.

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

Abstract: A method for semiconductor manufacturing is provided. The method includes defining a first cell level group comprising a first set of pattern features corresponding to a predetermined manufacturing process associated with an layout; determining a first number of cell units based on the first cell level group, wherein each of the first number of cell units is compatible with each other; defining a second cell level group comprising the first set of pattern features and a second set of pattern features; and determining a second number of cell units based on the second cell level group, wherein each of the second number of cell units is compatible with each other. The first set of pattern features and the second set of pattern features are arranged in responsive to sequential operations of the predetermined manufacturing process.

Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.

Abstract: In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.