Patents by Inventor Jung-Chan YANG

Jung-Chan YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369389
    Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: July 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Patent number: 12363982
    Abstract: A system for processing a layout of a semiconductor device includes a processor, and a computer readable storage medium. The processor is configured to execute instructions to generate an active region layout pattern extending in a first direction, generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern, generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns, generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns, and generate one or more mark layers. Each of the mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate a width of the corresponding source/drain layout pattern.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Syuan Ciou, Hui-Zhong Zhuang, Jung-Chan Yang, Li-Chun Tien
  • Patent number: 12341103
    Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Patent number: 12340165
    Abstract: A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.
    Type: Grant
    Filed: June 12, 2024
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Ting-Wei Chiang, Chi-Yu Lu
  • Patent number: 12324228
    Abstract: An integrated circuit is provided, including a first conductive pattern, at least one first conductive segment, and a first via. The first conductive pattern is disposed in a first layer and configured as a terminal of an inverter. The at least one first conductive segment is disposed in a second layer above the first layer and configured to transmit an output signal output from the inverter. The first via contacts the first conductive pattern and the at least one first conductive segment to transmit the output signal. An area, contacting the first conductive pattern, of the first via is smaller than an area, contacting the at least one first conductive segment, of the first via.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Jiann-Tyng Tzeng, Ting-Wei Chiang, Jung-Chan Yang, Stefan Rusu
  • Publication number: 20250169189
    Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a first gate, a first set of power rails, and a first set of vias. The first set of contacts overlaps the set of active regions, and a first and second cell boundary. The first gate overlaps the set of active regions, not overlapping the first and second cell boundary, and is between the first set of contacts. The first set of power rails is configured to supply a first or second supply voltage, and overlaps the first gate. The first set of vias is between the first gate and the first set of power rails, and electrically couples the first gate and the first set of power rails together. At least one active region of the set of active regions extends continuously through the first and second cell boundary.
    Type: Application
    Filed: January 21, 2025
    Publication date: May 22, 2025
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN
  • Publication number: 20250169190
    Abstract: A method for forming a semiconductor device includes forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the recess, wherein the first conductive line extends across the fin structure and wraps a first portion of the fin structure; forming a second conductive line in the same layer as the first conductive rail, wherein the second conductive line extends across the fin structure and contacts a second portion of the fin structure different from the first portion; and forming an isolation region on the substrate to separate the first conductive rail from the second conductive line.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 22, 2025
    Inventors: SHUN-LI CHEN, CHUNG-TE LIN, HUI-ZHONG ZHUANG, PIN-DAI SUE, JUNG-CHAN YANG
  • Patent number: 12302642
    Abstract: An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.
    Type: Grant
    Filed: July 1, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Kuo-Nan Yang
  • Publication number: 20250118674
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions arranged on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 10, 2025
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 12254261
    Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Sing Li, Jung-Chan Yang, Ting Yu Chen, Ting-Wei Chiang
  • Patent number: 12243914
    Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Lee-Chung Lu, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 12237322
    Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun-Li Chen, Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Jung-Chan Yang
  • Publication number: 20250056895
    Abstract: An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal electrically coupled to the gate terminal of the first transistor, and first and second terminals electrically coupled to each other.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 13, 2025
    Inventors: Yi-Jui CHANG, Jung-Chan YANG
  • Publication number: 20250056847
    Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, TING-WEI CHIANG, CHENG-I HUANG, KUO-NAN YANG
  • Publication number: 20250046719
    Abstract: A method of forming a semiconductor device includes forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to a doped region. The method further includes forming a via-to-via (V2V) rail which extends in a second direction angled with respect to the first direction, wherein the V2V rail overlaps at least of the first MD contact structure or the third MD contact structure. The method further includes forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail. The method further includes forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Jung-Chan YANG, Chi-Yu LU, Hui-Zhong ZHUANG, Chih-Liang CHEN
  • Patent number: 12211793
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 12205941
    Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen
  • Patent number: 12176394
    Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Lee-Chung Lu, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 12166029
    Abstract: An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jui Chang, Jung-Chan Yang
  • Patent number: 12159899
    Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Ting-Wei Chiang, Cheng-I Huang, Kuo-Nan Yang