Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.

Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: In this specification, a image decoding method is disclosed. The image decoding method of the present invention comprises, decoding block partition information of a current block included in a current picture, determining a partitioning scheme for the current block according to the block partition information and partitioning the current block using the partitioning scheme determined, wherein the partitioning scheme is determined according to whether the current block includes a boundary of the current picture.

Abstract: This patent presents a multidimensional space vector modulation (MDSVM) circuit formed by coupling a half-bridge logic control circuit not directly coupled to electronic components with at least three half-bridge logic control circuits coupled to electronic components. The half-bridge logic control circuit not directly coupled with any electronic components can form a full-bridge circuit with any other half-bridge logic control circuit coupled with electronic components. Therefore, users can further control the voltage difference between both ends of each electronic component separately and then individually control the strength and direction of current flowing through each electronic component and solving the problem of control attributed to the complexity of prior art.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

Abstract: A magnetic core according to one embodiment of the present invention includes a material formed of iron (Fe)-silicon (Si)-boron (B), wherein a mass percentage of Fe in a first surface, which is an upper surface, is different from a mass percentage of Fe in a second surface which is a side surface, and a ratio of the mass percentage of Fe in the first surface to a difference between the mass percentage of Fe in the first surface and the mass percentage of Fe in the second surface is in the range of 6 to 21.

Abstract: A processing machine (10) for building an object (11) from powder (12) includes a build platform (26A); a powder supply assembly (18) that deposits the powder (12) onto the build platform (26A) to form a powder layer (13); and an energy system (22) that directs an energy beam (22D) at a portion of the powder (12) on the build platform (26A) to form a portion of the object (11). The powder supply assembly (18) can include (i) a powder container (640A) that retains the powder (12); (ii) a supply outlet (639) positioned over the build platform (26A); and (ii) a flow control assembly (642) that selectively controls the flow of the powder (12) from the supply outlet (639).

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.

Abstract: A method of manufacturing a display device includes providing an adhesive material layer on a display panel, curing the adhesive material layer to form an adhesive layer, providing a cover layer on the adhesive layer, and adhering the cover layer to the adhesive layer, and a modulus of the adhesive layer at room temperature is in a range of about 103 Pa to about 106 Pa.

Abstract: The present invention relates to a video encoding/decoding method and apparatus. The video decoding method according to the present invention may comprise decoding filter information on a coding unit; classifying samples in the coding unit into classes on a per block classification unit basis; and filtering the coding unit having the samples classified into the classes on a per block classification unit basis by using the filter information.

Abstract: A consumer electronic device includes a battery module and a system chip. The battery module includes: battery cells, a heater adjacent to the battery cells, a battery management circuit coupled to the battery cells and the heater, and an electrical connector including an information transmission interface and a power transmission interface. The information transmission interface is coupled to the battery management circuit, and the power transmission interface is coupled to the battery cells. The system chip is coupled to the information transmission interface, and is configured to receive battery information from the battery management circuit through the information transmission interface. When a battery temperature of the battery information is lower than a first threshold, the system chip sends an activation signal to the battery management circuit through the information transmission interface, for the battery management circuit to activate the heater according to the activation signal.

Abstract: An image encoding/decoding method is disclosed. A method of decoding an image, the method comprising, deriving an intra prediction mode for a current block, decoding at least one original sample that is present in a rightmost column and a bottommost row (a bottom row) of the current block, constructing a reference sample by using the at least one decoded original sample and performing intra prediction on the current block by using the constructed reference sample.

Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.