Abstract: A plug includes a first member and a second member detachably connected to each other. The first member includes four conductors, which are separated from each other. The third and fourth conductors are selectively electrically connected to the first and second conductors, respectively. The second member includes four pins. The first and second pins are electrically connected to the first and second conductors, respectively, and are selectively electrically connected to the third and fourth conductors, respectively. The third and fourth pins are electrically connected to the first and second pins, respectively. The first and second pins are separated from each other, and the third and fourth pins are separated from each other. A power supply configured with the plug and a power connector are also provided.

Abstract: An adapter includes a rectifying unit, a power factor correction unit, a standby circuit, a load-connecting detection circuit, a first power conversion circuit, a second power conversion circuit and an auxiliary voltage control circuit. When a load apparatus is connected to the adapter, a first ground side of the first power conversion circuit is short-circuited to a second ground side of the second power conversion circuit, so that the load-connecting detection circuit is turned on and sends out a first signal. After the auxiliary voltage control circuit receives the first signal, the auxiliary voltage control circuit is turned on to drive the first power conversion circuit and the second power conversion circuit, so that the first power conversion circuit and the second power conversion circuit start to convert a first voltage into a first output voltage and a second output voltage.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.

Abstract: A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: An ecosystem operated in a plant having a drying unit is provided. The ecosystem includes: a regenerative thermal oxidization unit for processing a waste gas to produce a hot gas; a first hot gas pipeline connected to the regenerative thermal oxidization unit and the drying unit, wherein the hot gas is transferred from the regenerative thermal oxidization unit to the drying unit via the first hot gas pipeline; a heat recovery unit disposed at the first hot gas pipeline to absorb heat from the first hot gas pipeline; an absorption refrigeration unit connected to a target to be cooled; and a hot liquid pipeline connected to the heat recovery unit and the absorption refrigeration unit, wherein the heat recovery unit transfers heat from the first hot gas pipeline to the absorption refrigeration unit via the hot liquid pipeline to actuate the absorption refrigeration unit to cool the target.

Abstract: This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.

Abstract: A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.

Abstract: This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.

Abstract: A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.

Abstract: A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.

Abstract: A low electric field source erasable non-volatile memory unit includes a substrate having a source diffusion region and a drain diffusion region. The source diffusion region includes a heavily-doped region and a lightly-doped region extending. A first dielectric layer and a tunnel dielectric layer are formed on the substrate. The tunnel dielectric layer includes a lower face contiguous to or partially overlapped with the lightly-doped region of the source diffusion region. A select gate and a floating gate are respectively formed on the first dielectric layer and the tunnel dielectric layer. The floating gate includes a source side edge contiguous to or partially overlapped with the lightly-doped region and misaligned from the heavily-doped region by a distance. A second dielectric layer and a control gate are formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: A non-volatile memory unit includes a substrate on which a source diffusion region and a drain diffusion region are formed. A first dielectric layer and a tunnel dielectric layer are formed between the source diffusion region and the drain diffusion region, are respectively on the drain diffusion region side and the source diffusion region side, and are connected to each other. A select gate is formed on the first dielectric layer. A source insulating layer is formed on the source diffusion region. The tunnel dielectric layer extends to the source diffusion region and is connected to the source insulating layer. A floating gate is formed on a face of the tunnel dielectric layer and a face of the thicker source insulating layer. A control gate is formed on the floating gate. The control gate and the floating gate are insulating to each other by the second dielectric layer.

Abstract: An ecosystem operated in a plant having a drying unit is provided. The ecosystem includes: a regenerative thermal oxidization unit for processing a waste gas to produce a hot gas; a first hot gas pipeline connected to the regenerative thermal oxidization unit and the drying unit, wherein the hot gas is transferred from the regenerative thermal oxidization unit to the drying unit via the first hot gas pipeline; a heat recovery unit disposed at the first hot gas pipeline to absorb heat from the first hot gas pipeline; an absorption refrigeration unit connected to a target to be cooled; and a hot liquid pipeline connected to the heat recovery unit and the absorption refrigeration unit, wherein the heat recovery unit transfers heat from the first hot gas pipeline to the absorption refrigeration unit via the hot liquid pipeline to actuate the absorption refrigeration unit to cool the target.

Abstract: A regulating apparatus with soft-start and fast-shutdown function is applied to a voltage-supplying apparatus. The regulating apparatus includes a soft-start and fast-shutdown circuit, a regulating circuit, and a ground circuit. When voltages are supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is connected to ground, so that the starting time of the regulating circuit is delayed by the soft-start and fast-shutdown circuit. When voltages are not supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is not connected to ground, so that the regulating circuit is shut down fast by the soft-start and fast-shutdown circuit.

Abstract: A regulating apparatus with soft-start and fast-shutdown function is applied to a voltage-supplying apparatus. The regulating apparatus includes a soft-start and fast-shutdown circuit, a regulating circuit, and a ground circuit. When voltages are supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is connected to ground, so that the starting time of the regulating circuit is delayed by the soft-start and fast-shutdown circuit. When voltages are not supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is not connected to ground, so that the regulating circuit is shut down fast by the soft-start and fast-shutdown circuit.

Abstract: A multi-channel LED driving system includes a power adapter, a rectifying and filtering unit, a plurality of LED strings, and a plurality of linear regulators, a CC/CV controller, an optically coupled isolator and a PWM controller. The CC/CV controller detects the conducting currents flowing though the LED strings and DC voltage source outputting from the rectifying and filtering unit, and provides voltage compensation of the power adaptor. In addition, the linear regulators slightly modulate the current difference between the LED strings to achieve current-sharing control, thus stabilize the illuminating brightness generating by the LED.

Abstract: A multi-channel LED driving system includes a power adapter, a rectifying and filtering unit, a plurality of LED strings, and a plurality of linear regulators, a CC/CV controller, an optically coupled isolator and a PWM controller. The CC/CV controller detects the conducting currents flowing though the LED strings and DC voltage source outputting from the rectifying and filtering unit, and provides voltage compensation of the power adaptor. In addition, the linear regulators slightly modulate the current difference between the LED strings to achieve current-sharing control, thus stabilize the illuminating brightness generating by the LED.

Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.