Patents by Inventor Jung Chao
Jung Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230383221Abstract: A method for making an alcohol-containing food product comprises combining: (a) a first aqueous solution that includes a multivalent salt, one or more liquid alcohol additives and a thickening agent; with (b) a second aqueous solution that includes an alginate bath. The combination uses extrusion machinery to mass produce spherical beads, less than about 20 mm in typical diameter, with a liquid alcohol center encapsulated in a gelled outer shell. The resulting end product should be collected and stored in a third aqueous solution that maintains similar properties to the first aqueous solution and one or more liquid alcohol additives.Type: ApplicationFiled: March 20, 2023Publication date: November 30, 2023Inventors: SHIAN-JUNG CHAO, YUN-SHI CHEN
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Publication number: 20230335642Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include transistors formed in a (100) surface of a semiconductor substrate wherein a channel is oriented in a <100> direction. The transistors further include one or more strain induced dislocations adjacent to a channel.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventors: Toshihiko Miyashita, Jung Chao Chiou
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Patent number: 9744146Abstract: A method for alleviating at least one of the disturbance of bile acid metabolism, the disturbance of amino acid metabolism, and the disturbance of gut microbiota metabolism in a subject, comprising administering to the subject a composition or a health food comprising an active component selected from the group consisting of gallic acid, a pharmaceutically acceptable salt of gallic acid, a pharmaceutically acceptable ester of gallic acid, and combinations thereof.Type: GrantFiled: October 31, 2014Date of Patent: August 29, 2017Assignee: CHINA MEDICAL UNIVERSITYInventors: Wen-Huang Peng, Li-Heng Pao, Jung Chao, Hao-Yuan Cheng, Meng-Shiou Lee
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Publication number: 20160186081Abstract: An environmental protection liquid fuel generator, in which the fuel oil generator is a structure made from a receiving device, an esterification device, a first standing separation device, a compression distillation device, an acid-base neutralization device, a second standing separation device, and a decompression distillation device. A mixed proportion of a vegetable oil and an alkide (catalyzing enzyme) is placed into the fuel generator, and the esterification device is used to increase electron affinity and accelerate the reaction rate, thereby enabling the distillation of low polluting and low sulfur containing environmental protection fuel oil.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Chih-Jung CHAO, Lian-Nak TI
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Publication number: 20150174087Abstract: A method for alleviating at least one of the disturbance of bile acid metabolism, the disturbance of amino acid metabolism, and the disturbance of gut microbiota metabolism in a subject, comprising administering to the subject a composition or a health food comprising an active component selected from the group consisting of gallic acid, a pharmaceutically acceptable salt of gallic acid, a pharmaceutically acceptable ester of gallic acid, and combinations thereof.Type: ApplicationFiled: October 31, 2014Publication date: June 25, 2015Inventors: Wen-Huang Peng, Li-Heng Pao, Jung Chao, Hao-Yuan Cheng, Meng-Shiou Lee
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Patent number: 7598595Abstract: A nanoporous antireflection coating preparation method. A sol-gel precursor solution containing an organic template is coated onto a substrate. The sol-gel precursor solution containing the organic template is dried into a film. The organic template within the film is then removed to form a nanoporous antireflection coating. In preferred embodiments, the organic template is removed by UV—O3 treatment at ambient temperature.Type: GrantFiled: June 16, 2006Date of Patent: October 6, 2009Assignee: Industrial Technology Research InstituteInventors: Kuei-jung Chao, Kuo-ying Huang, Shu Fang Chen
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Publication number: 20080083157Abstract: An environmental protection synthetic low sulphur fuel oil that uses a proportional mixture of vegetable oil and a catalyzing enzyme (decane, 11 alkane, 12 alkane) as a substitute for high polluting high grade diesel oils to achieve required flash point and reduce sulphur content, and which can be used as a green environmental protection additive agent to high grade diesel oil, thereby achieving the objective of providing a method that effects environment protection.Type: ApplicationFiled: October 6, 2006Publication date: April 10, 2008Inventor: Chih-Jung Chao
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Publication number: 20080014355Abstract: A method for preparing a palladium-containing layer comprises the steps of cleaning a top surface of the porous substrate, modifying the top surface of the porous substrate to form a planar surface, performing a seeding process on the planar surface to adhere palladium nanoparticles on the planar surface and performing an electroless plating process to form the palladium-containing layer on the planar surface. The step of modifying the top surface of the porous substrate includes filling holes of the porous substrate with aluminum oxide particles, coating a sol-gel containing aluminum oxide or silicon oxide on the top surface of the porous substrate, The step of performing a seeding process on the planar surface includes exposing the planar surface of the porous substrate in a nanocolloidal solution having dispersed palladium nanoparticles derived from a palladium-containing species and a surfactant.Type: ApplicationFiled: July 12, 2006Publication date: January 17, 2008Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Kuei Jung Chao, Chi Yuan Chang, Wei Chih Lin
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Publication number: 20070141854Abstract: A nanoporous antireflection coating preparation method. A sol-gel precursor solution containing an organic template is coated onto a substrate. The sol-gel precursor solution containing the organic template is dried into a film. The organic template within the film is then removed to form a nanoporous antireflection coating. In preferred embodiments, the organic template is removed by UV—O3 treatment at ambient temperature.Type: ApplicationFiled: June 16, 2006Publication date: June 21, 2007Inventors: Kuei-jung Chao, Kuo-ying Huang, Shu Fang Chen
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Patent number: 6733828Abstract: A method of confined synthesis of nanostructured material inside a mesoporous material. The method includes the step of providing mesoporous material having uniform and ordered mesopores. Next, a monolayer of charged functional group is attached on the pore surface of mesoporous host material by reacting with functional molecule. A oppositely-charged molecule is incorporated into the confined space of mesoporous material by either ion exchange or incipient wetness impregnation. Finally, the incorporated molecule is reduced or oxidized or further reacted with secondarily-incorporated molecule to form nanostructured material in mesoporous material.Type: GrantFiled: January 29, 2002Date of Patent: May 11, 2004Inventors: Kuei-Jung Chao, Chia-Min Yang
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Publication number: 20030152759Abstract: A method of confined synthesis of nanostructured material inside a mesoporous material. The method includes the step of providing mesoporous material having uniform and ordered mesopores. Next, a monolayer of charged functional group is attached on the pore surface of mesoporous host material by reacting with functional molecule. A oppositely-charged molecule is incorporated into the confined space of mesoporous material by either ion exchange or incipient wetness impregnation. Finally, the incorporated molecule is reduced or oxidized or further reacted with secondarily-incorporated molecule to form nanostructured material in mesoporous material.Type: ApplicationFiled: January 29, 2002Publication date: August 14, 2003Inventors: Kuei-Jung Chao, Chia-Min Yang
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Patent number: 6376382Abstract: A method for forming an opening is provided. The method contains forming a dielectric layer on the substrate. The dielectric layer is patterned to form a first-stage opening. A carbonic-polymer (C-polymer) concentration controlling treatment is performed to obtain a proper C-polymer concentration, which can be raised, reduced, or even down to a zero concentration. After the proper C-polymer concentration is obtained, a next-stage opening is formed by another step of etching. The C-polymer concentration controlling treatment and the etching process with a new condition for each step can be repeated until a desired opening is formed.Type: GrantFiled: December 30, 1998Date of Patent: April 23, 2002Assignee: United Microelectronics Corp.Inventors: Jung-Chao Chiou, Hsiao-Pang Chou
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Patent number: 6277727Abstract: This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask.Type: GrantFiled: October 20, 1999Date of Patent: August 21, 2001Assignee: United Microelectronics Corp.Inventors: Chien-Li Kuo, Jung-Chao Chiou
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Patent number: 6277685Abstract: The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole.Type: GrantFiled: October 20, 1999Date of Patent: August 21, 2001Assignee: United Microelectronics Corp.Inventors: Benjamin Szu-Min Lin, Jung-Chao Chiou, Chin-Hui Lee, Chuan-Fu Wang
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Patent number: 6251725Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole.Type: GrantFiled: January 10, 2000Date of Patent: June 26, 2001Assignee: United Microelectronics Corp.Inventors: Jung-Chao Chiou, Te-Yuan Wu, Chuan-Fu Wang
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Patent number: 6214747Abstract: A method for forming an opening in a semiconductor device is provided. A silicon-oxy-nitride layer is formed on a dielectric layer and then a photoresist layer with a first opening is formed on the silicon-oxy-nitride layer. A polymer film is formed on sidewalls of the first opening. A second opening narrower than the first opening is formed in the dielectric layer with the photoresist layer and the polymer film.Type: GrantFiled: October 28, 1999Date of Patent: April 10, 2001Assignee: United Microelectronics Corp.Inventors: Hsiao-Pang Chou, Jung-Chao Chiou
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Patent number: 6204117Abstract: A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H3PO4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H3PO4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.Type: GrantFiled: July 14, 1999Date of Patent: March 20, 2001Assignee: United Microelectronics Corp.Inventors: Jung-Chao Chiou, Chuan-Fu Wang
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Patent number: 6197700Abstract: A method of fabricating a bottom electrode for a capacitor is described in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. A node contact window opening is formed in the dielectric layer, exposing the landing pad, and a conformal first conductive layer is formed on the substrate. After a specially patterned mask layer is formed and the exposed first conductive layer is removed, an extended portion is formed connecting to the conductive layer to complete the fabrication of the columnar bottom electrode for a capacitor.Type: GrantFiled: August 16, 1999Date of Patent: March 6, 2001Assignee: United Microelectronics Corp.Inventors: Chuan-Fu Wang, Jung-Chao Chiou
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Patent number: 6190956Abstract: A method for forming a capacitor structure of semiconductor is disclosed. The method includes the following steps. First of all, a first oxide layer is deposited. A first nitride layer is formed. Consequentially, a portion of the first nitride layer and a portion of the first oxide layer are all etched. Then, the first polysilicon layer is formed. The portion of the first polysilicon layer is reduced to a specified thickness. Next, boron phosphorus silicon glass layer blankly and conformably is formed. Then, a portion of said boron phosphorus silicon glass layer is etched. A second polysilicon layer is deposited. Next, a portion of the second polysilicon layer is etched back. Next, the boron phosphorus silicon glass layer is etched. Then, the first polysilicon layer is etched back. A second nitride layer is formed. Next, a second oxide layer is deposited. Finally, a conductive layer is formed as a top plate of capacitor, whereby a capacitor structure is completed and there are a top plate and a bottom plate.Type: GrantFiled: January 31, 2000Date of Patent: February 20, 2001Assignee: United Microelectronics Corp.Inventors: Jhy-Jyi Sze, Jung-Chao Chiou
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Patent number: 6187669Abstract: This invention provides a method of forming a node contact with self-alignment on a semiconductor wafer. The wafer comprises a substrate, a dielectric layer, and a first and a second bit lines. A first side wall of the first bit line is adjacent to a second side wall of the second bit line and comprises a first region and two second regions adjacent to the first region. The distance between the first region and the second side wall is greater than a predetermined value and the distance between the two second regions and the second side wall is less than the predetermined value. A second insulating layer is formed on the dielectric layer and two bit lines to form a groove over the gap between the first region and the second side wall. A first anisotropic etching is performed to extend the bottom of the groove down to the dielectric layer.Type: GrantFiled: September 8, 1999Date of Patent: February 13, 2001Assignee: United Microelectronics Corp.Inventors: Jung-Chao Chiou, Benjamin Szu-Min Lin